Neuromorphic Computing with Resistive Memory and Bayesian Machines

Abstract

Bio-inspired computing with memristors and neuristors offers promising pathways to energy-efficient intelligence. This work reviews toolkits for implementing spiking neural networks and Bayesian machine learning directly in hardware using these emerging devices. We first demonstrate that normally passive memristors can exhibit neuristor-like oscillatory behavior when heating and cooling is taken into account. Such oscillations enable spike-based neural computing. We then summarize recent works on leveraging intrinsic switching stochasticity in memristive devices to physically embed Bayesian models and perform in-situ probabilistic inference. While still facing challenges in endurance, variation tolerance, and peripheral circuitry, this co-design approach combining tailored algorithms and nanodevices could enable a new class of ultra-low power brain-inspired intelligence tolerant to uncertainty and capable to learn with small datasets. Longer-term, hybrid CMOS-memristor systems with sensing/actuation may provide fully adaptive Bayesian edge intelligence. Overall, the confluence of probabilistic algorithms and memristive hardware holds promise for future electronics combining efficiency, adaptability, and human-like reasoning. Academic innovations exploring this algorithm-hardware co-design can lay the foundation for this emerging paradigm of probabilistic cognitive computing.

1. Introduction

Brain is one of the most complex objects known to humanity with most of it’s functionality yet to be discovered. The complexity of brain lays in it’s self-organization that goes on through lifetime where individual neurons constantly seek new connections with proximate and distant neurons growing new and destroying old and unused synaptic connections. Each neural cell is surrounded by an environment full of ions with neuron’s membrane serving as a barrier preventing an uncontrolled charge to flow through it. Instead the ion channels on the surface of the neuron opens and closes at specific times when concentration of particular charge exceeds membrane threshold that results in membrane depolarization, causing transmission of spiking signal over synapse as shown in Figure 1. The spiking signal is then converted into chemical signal via combination of neuromediators and transmitted further to postsynaptic cell. The frequency and density of the stimulation from presynaptic neuron affects the probability of activation of postsynaptic neuron, whereas this neuron contributes to signal propagation to other downstream neurons.

Figure 1.

Biological network and it’s approximation with memristors. (a) Biological network with presynaptic and postsynaptic neurons with a spiking cell depolarization signal traveling along axon (image from https://scidraw.io/drawing/610). (b) An approximated artificial network with memristors acting as synapses. (c) Crossbar array with artificial memristive synapses as an efficient approach to neuromorphic computation.

In biological neurons excitation from one neuron propagates to downstream neurons in a branching fashion, frequently with probabilities below 1, which is a signature of subcritical interaction [1]. In other words it is unlikely that signal from a single neuron will be noticed by large number of neighbor neurons and will frequently result in a random-walk-like pathway that fades away after few dozens of cells but can propagate for many more longer steps. This subcritical interaction between neurons, facilitates the highest possible efficiency of information transmission in biological neural network [2] and increases it’s dynamic range [3].

Configuring networks of nonlinear neuron-like elements enables efficient and flexible parallel analog computation, which helps biological organisms survive by solving complex problems such as finding food and avoiding threats [4]. In particular, the nonlinear interactions between neurons are facilitated by the brain’s adaptive plasticity, allowing synapses to strengthen or weaken [5]. This synaptic plasticity enables a variety of arithmetical operations on neural signals [6], including multiplication, addition, subtraction, convolution, and more [7]. By leveraging similar principles, artificial neural networks aim to achieve brain-like flexibility and computational power.

Mathematically, a biological neural network can be approximated as a nonlinear function that accepts any number of weighted inputs from upstream neurons [4]. This function applies a threshold to sum the inputs, converting them into a scalar neuronal activation value (Figure 1) [8]. Even simple artificial neural network models based on this principle, using synapses as real-valued connection weights and neurons as summators with thresholding transfer functions, have achieved tremendous successes in applications like image recognition [9], natural language processing [10], and content generation [11]. The ability of artificial neural networks to perform complex information processing tasks has sparked a revolution in the information era [12]. By emulating aspects of brain computation, techniques like deep learning are powering advances in fields from computer vision to healthcare [13].

However, modern artificial neural networks only imitate a fraction of biological neural network functionality, primarily neuron activation functions and synaptic weight connections. An interesting technique borrowed from biology is randomly “dropping out” weights during training, which regularizes artificial networks by improving their robustness [14, 15]. This weight dropout technique is surprisingly effective, and is now widely used when training neural networks across many applications, including large language models like GPT [16]. Randomly disabling connections seems to mimic the noisy yet fault-tolerant nature of biological neural processing [14]. While artificial networks do not yet match the full complexity of biological computation, techniques like weight dropout demonstrate how we can take inspiration from neuroscience to improve deep learning.

While deep artificial neural networks have achieved remarkable results on narrow tasks, their simple neuron models and matrix multiply operations remain primitive compared to biological brains. Modern deep learning approaches lack the adaptability, fault tolerance, and uncertainty handling of actual neural circuits. Their massive data requirements and susceptibility to unintended bias also contrast the efficiency and versatility of biological learning. Additionally, approximations of spiking dynamics in artificial networks are quite basic compared to rich temporal processing in real neurons. Unlike fault-tolerant biological hardware, artificial neural network implementations are not inherently robust. These limitations motivate exploring alternative bio-inspired computing paradigms. This work reviews recent progress on leveraging memristive devices to realize more efficient and robust neural computing. We explore the active properties arising in passive memristor networks, which enable spiking oscillations similar to neuristors. We also discuss implementing Bayesian inference directly in memristive hardware, achieving efficient learning from limited data while avoiding overfitting. By emulating additional facets of biological neural computation, from spiking dynamics to probabilistic reasoning, memristor-based architectures could provide a path towards more adaptive, resilient, and low-power brain-inspired intelligence.

2. Neuromorphic computing with memristors and neuristors

2.1 Memristors

Memristors are passive circuit elements that exhibit resistance based on the history of applied voltage or current. This memristance arises in devices with mobile cationic or anionic type of carriers that drift within an insulating layer under an electric field, altering the internal resistance [17, 18]. For example, in cation-based memristors, such as chalcogenides ${\mathrm{Ag}}_2\mathrm{S}$ or ${\mathrm{Cu}}_2\mathrm{S}$ applying a positive voltage causes Ag⁺ or ${\mathrm{Cu}}_{2^{+}}$ ions to drift towards the cathode, forming conductive bridges that decrease resistance [19]. Similarly, reversing the polarity of the voltage causes break-down the conductive filaments redusing the conductivity of the device. The memristance depends on the extent of ionic transport within the device [20]. Compared to CMOS transistors, memristors offer improved energy efficiency and density, with switching energies down to 1 fJ per bit, and can retain non-volatile memory states even after power is removed [21]. However, switching speeds are often slower than solid-state electronics, ranging from nanoseconds up to milliseconds for full ion migration [22]. Further advances in materials and integration will help unleash the potential of memristors for low-power neuromorphic computing.

One widely studied memristor material is titanium dioxide $\left({\mathrm{TiO}}_2\right)$ thin films, which exhibit voltage-controlled transport of oxygen vacancies within the oxide layer to alter resistance states [23, 24]. For example, in $\mathrm{Pt}/{\mathrm{TiO}}_2/\mathrm{Pt}$ devices, applying a positive voltage causes ${\mathrm{O}}_{2^{-}}$ ions to drift towards the anode, creating oxygen vacancy rich filaments that locally increase conductivity [25]. Reversing the bias causes annihilation of these Magnéli filaments, increasing the device resistance [26]. The time for switching between the high and low resistance states in ${\mathrm{TiO}}_2$ memristors is typically on the order of 100 ns for filament formation or rupture [27]. However, the full timescale over which the memristance evolves can range from microseconds for small perturbations up to seconds for reaching extremal resistances, depending on voltage amplitude, film thickness, and device structure [28, 29]. Further research on interfaces and doping seeks to improve the stability and tunability of TiO₂-based memristors for neuromorphic computing applications.

The memristance of a basic memristive device can be modeled as a thin film with thickness D, as described by Strukov et al. [18]. The memristance M depends on the internal state variable x, which represents the position of dopants or effective filament length within the device shown in Eqs. (1) and (2).

Here, ${\mathrm{R}}_{\mathrm{ON}}$ is the low resistance state when x = 1 corresponding to maximum doping or full filament formation. ${\mathrm{R}}_{\mathrm{OFF}}$ is the high resistance state when x = 0 corresponding to no doping or an open filament gap. The internal state variable x evolves according to Eq. (2) where F is a function describing the rate of filament growth or dopant drift under an applied voltage V and time t resulting in current I. Eqs. (1) and (2) link the internal material dynamics to the externally measurable memristance M, which can vary continuously between ${\mathrm{R}}_{\mathrm{ON}}$ and ${\mathrm{R}}_{\mathrm{OFF}}$ depending on the value of x. To simplify numerical integration, a window function is added, that is denoted by F(x). This basic model captures the essence of resistance switching in memristive devices based on filamentary or dopant migration mechanisms.

$$M=R_{\mathit{on}}\frac{x\left(t\right)}{D}+R_{\mathit{off}}\left(1-\frac{x\left(t\right)}{D}\right)$$E1

$$\frac{\mathit{dx}}{\mathit{dt}}=\mu \frac{R_{\mathit{on}}}{D}\mathit{\text{IF}}\left(x\right)$$E2

While an individual memristor acts as a passive device, interconnecting memristors in networks can lead to remarkable emergent properties. As shown in Figure 2, we simulated a network of randomly oriented memristive nanowires governed by Eqs. (1) and (2). When subjected to oscillating voltage patterns, this network exhibited negative differential resistance (NDR)-meaning the current actually decreased in some voltage ranges. This NDR normally only occurs in active devices undergoing metal–insulator transitions. It enables oscillatory signal generation and neuristor-like spiking behavior. The emergence of NDR in these simulations suggests that networks of passive memristors can display unusual active characteristics. This arises from the complex interactions within the network topology. While individual memristors obey simple dynamics, connecting them together leads to more complex phenomena like NDR.

Figure 2.

Triangular voltage sweeps through a network of 879 randomly distributed memristors exhibiting a pattern of negative differential resistance.

The emergent active properties arising in networks of passive memristors are intriguing, there remain open questions about fully characterizing and exploiting such effects for neuromorphic computing. However, progress has also been made in engineering truly active memristive devices that functionally mimic spiking oscillations in biological neurons. These “neuristor” devices incorporate additional structures and physical effects beyond basic memristance to achieve neuron-like dynamics, moving beyond simply interconnecting passive memristors.

2.2 Neuristors

Neuristor is another class of two-terminal electronic devices that aim to functionally mimic dynamics of biological neuron. Neuristor was conceptualized in 1960s by Crane et al., that proposed a computation system with electrical elements exhibiting fatigue in order to imitate decay of charge propagation in neural soma [30, 31]. However, first attempts of electric implementation of neuristors was not scalable due to the need for inductors or bipolar thyristors [32, 33]. At around the same time, a novel threshold switching property of common oxides such as ${\mathrm{VO}}_2$, VO and TiO was reported by Morin et al. [34] that showed an abrupt change in conductivity in these materials upon reaching particular temperatures as a result of metal to insulator transitions. More than half a century later this property was used by Pickett et al. to show the first neuristor device based on ${\mathrm{NbO}}_2$, that demonstrated insulator-to-metal transitions that exhibited neuron-like oscillations without silicon transistors [35, 36] using only resistors and capacitors for internal state storage.

Another variant of neuristors was also reported based on ${\mathrm{VO}}_2$ [37]. ${\mathrm{VO}}_2$ is a termochromic material that undergoes an abrupt resistance switch around 340 K with characteristic color change due to a structural phase from semiconducting monoclinic to metallic rutile phase monoclinic [38, 39]. A typical I-V characteristics of a nanoscale devices shown in Figure 3. In this configuration, a small amount of nanoscale ${\mathrm{VO}}_2$ material was sandwiched between two copper conductors in a 100 um diameter cavity. While triangular voltage sweep exhibited metal–insulator transitions between 10 and 20 V, the triangular current driven regime (y axis) showed negative differential resistance with characteristic.

Figure 3.

Resistive switching of ${\mathit{VO}}_{\mathit{2}}$ device. (a) Triangular voltage sweep setup, showing metal–insulator phase transition (b) triangular current sweep setup, showing a characteristic negative differential resistance.

Thin film ${\mathrm{VO}}_2$ neuristors have exhibited spiking oscillations and threshold firing behavior analogous to action potentials in neurons [40, 41, 42]. The resistance transition in these threshold switching materials can be induced thermally, providing a means to modulate neuronal spiking patterns without relying solely on electrical bias like traditional memristors.

Recently a caloritronic neuristor was reported which relies on the low temperature of metal–insulator phase transitions in ${\mathrm{VO}}_2$ that allowed to eliminate capacitors needed to store internal state using only joule heating from a proximate resistor to move neuristor transition state closer to the phase transition or far away from it [43]. The reported device exhibited spiking with remarkable similarity to biological cells, namely Hodgkin-Huxley neuron model that opens opportunities for novel high-density neuromorphic computing [44].

Metal–insulator transitions enable spiking oscillations in neuristors, but they are not the only pathway. As we demonstrate, modifying the dynamics of plain memristors to include Joule heating and Newtonian cooling effects can also elicit oscillations. With carefully balanced thermal feedback, even simple memristive devices can exhibit self-sustaining spikes without undergoing a phase change.

Below we provide a model that could be used to simulate oscillations with a variant of NDR in a plain memristive nanowire with Joule heating and Newtonian cooling [45, 46, 47]. The parameters are depicted in Table 1 while modified memristor equations with cooling and heating terms are provided in Eqs. (3) and (4).

$R_{\mathit{ON}}$	$1\times {10}^4\mathrm{\Omega }$
$R_{\mathit{OFF}}$	$16\times {10}^5\mathrm{\Omega }$
D	10 nm
$\mu$	$1\times {10}^8{\mathrm{nm}}^2/\mathrm{s}/\mathrm{V}$
$\mathrm{ϵ}$	$1\times {10}^{-3}$
$w_0$	0
$\mathcal{T}$	0.01 s (period)
p	10
$\tau$	$1\times {10}^2$
$\rho$	$10.5\mathrm{kg}/{\mathrm{m}}^3$
c	240 J/kg/K
$\sigma$	$6.3\times {10}^7\mathrm{S}/\mathrm{m}$
A	$2\pi {\left(100\times {10}^{-9}\right)}^2{\mathrm{m}}^2$ (wire cross section area)
$T_c$	300 K

Table 1.

Memristor model parameters.

$$R\left(w\right)=\left(R_{\mathit{OFF}}-\left(R_{\mathit{OFF}}-R_{\mathit{ON}}\right)\ast w/D\right)$$E3

$$\begin{array}{r}\frac{\mathit{dw}}{\mathit{dt}}=\mu \frac{R_{\mathit{ON}}}{D^2}i-\frac{1}{\tau }\frac{w}{D}-\frac{1}{{10}^{-4}}\left(T-T_c\right)\frac{w}{D}\\ \frac{\mathit{dT}}{\mathit{dt}}=\frac{i^2}{\mathit{\rho c\sigma }{A}^2}-\frac{1}{{10}^{-4}}\left(T-T_c\right)\end{array}$$E4

The resulting state variable spiking signal generation is depicted in Figure 4 where a rounded-corner square voltage pulse set across the device forces it to generate a packet of four spikes in the state variable w. Interestingly, that spiking is generated due to the interplay of cooling, heating and state change and is governed only by the system of two first order ordinary differential equations.

Figure 4.

Simulation of spiking in a memristive nanowire that undergoes simultaneous Newtonian cooling and Joule heating.

Even more interesting behavior of this system can be observed when driven by a periodic signal. In particular when driven by $sin\left(\frac{2\mathit{\pi t}}{T}\right)$ the resulting oscillations become chaotic as shown in Figure 5. These temporal chaotic oscillations could be an alternative approach to stochastic computing as was proposed previously [48].

Figure 5.

Simulation of chaotic spiking in a memristive nanowire that undergoes simultaneous Newtonian cooling and Joule heating when driven with periodic voltage signal. (a) The IV characteristics of the device showing sporadic current spikes that result in rapid heating and followed by current drop due to the state switch (b) resulting change in state variable $\omega$ under influence of periodic voltage stimulation (c) the relationship between current and wire temperature (d) combined overview of current spiking and temperature as function of time.

Further investigation is required to confirm these type of oscillations in passive memristive devices with some insights highlights to approaches previously reported elsewhere [19].

However, the underlying physics of neuristors and memristors both involve modulating material resistivity to achieve analog memory states. Combining these devices in crossbar arrays enables dense neuromorphic systems that leverage bio-inspired computing principles [49]. The development of neuristors expands the toolkit for hardware-based neural networks beyond standard memristive elements providing environment for neuromorphic computing.

Unlike artificial neural networks, which use simplified rate-based neurons and static synaptic weights, neuristors directly mimic the rich temporal spiking dynamics of biological neurons. Rather than approximating spikes as averaged rates, neuristors exhibit self-sustaining oscillations and action potential-like firing patterns. This enables neuristor-based systems to capture the timing and rhythms of boinspired neuromorphic computation, which convey valuable information lost in rate-based Artificial Neural Network (ANN) models. As a result, neuristor networks have the potential to achieve brain-like capabilities beyond merely efficient statistical pattern recognition, such as complex temporal processing, real-time adaptability, and self-awareness [50]. While challenging to perfect, approximating both the architecture and temporal dynamics of biological cognition could enable revolutionary advances in artificial intelligence, beyond the constraints of feedforward deep learning. Looking forward, combining neuristor-based spiking dynamics with probabilistic modeling through Bayesian computing could provide the missing ingredients for fully brain-inspired intelligence.

2.3 Bayesian computing with stochastic memristors

While the goal for conventional neural networks is to learn a static weight, in Bayesian neural networks the weight is a distribution as shown in Figure 6. This is a one step towards biologically plausible neural networks as in biological synapses weights are modulated via chemical messengers across the synapse [7]. The complex balance and timing of different neurotransmitters binding to postsynaptic receptors thus encodes the weighting or strength of each synapse [51]. Therefore with their reliance on probabilistic inference and dynamic reweighting of connections, Bayesian neural networks may more closely reflect the uncertainty, adaptability, and neurotransmitter-modulated plasticity inherent in biological neural circuits than conventional artificial neural networks with static synaptic weights.

Figure 6.

Comparing ANNs to Bayesian Neural Networks (BNNs). ANNs store exact weights that makes them easy to overfit to data or being overconfident. BNNs on the other hand store weight distribution, that allows this network to learn from smaller datasets, while making them more robust and resistant to overfitting.

Recently, Harabi and colleagues developed an innovative memristor-based architecture to perform Bayesian inference entirely in hardware [52]. The system stores likelihood values distributed across separate arrays of hafnium oxide memristors, leveraging their non-volatile memory capability. These likelihood arrays connect with digital logic to physically encode the topology of a Bayesian network. Each memristor is operated as a binary device, programmed to a high or low conductance state to represent a probability value. Observations presented to the system essentially act as addresses, selecting the appropriate likelihoods to read from each array. The authors use stochastic computing techniques, generating random bit streams from the read likelihoods which get multiplied locally using AND gates. This architecture minimizes data movement. The prototype chip contained 2048 memristors and CMOS circuits which successfully performed inference. Simulations of a larger system showed orders of magnitude improvement in energy efficiency over a microcontroller implementation for a gesture recognition task. By mapping Bayesian networks directly into mixed-signal hardware using distributed memristor memory, this innovative work achieved significant acceleration and power savings compared to von Neumann architectures. It provides a blueprint for embedding sophisticated probabilistic reasoning on low-power edge devices.

At a high level, the Bayesian machine is implementing Bayes’ theorem to compute posterior probabilities as shown in Eq. (5):

$$\mathrm{P}\left(\text{Hypothesis}|\text{Data}\right)\propto \mathrm{P}\left(\text{Data}|\text{Hypothesis}\right)\mathrm{x}\mathrm{P}\left(\text{Hypothesis}\right)$$E5

More specifically in statistics language Eq. (5) translates into: Posterior ∝ Prior × Likelihood. Where likelihood is the prior probability of each hypothesis, stored in the “prior” memristor arrays. Prior is the likelihood of the observed data under each hypothesis, stored in the “likelihood” memristor arrays. The posterior is probability of each hypothesis given the data, computed by the Bayesian machine.

To perform this calculation:

1. The observed data acts as an address to look up the likelihood values from each likelihood array.

2. These likelihoods get converted to binary bit streams by comparison to random numbers.

3. The prior values are similarly converted to bit streams.

4. The bit streams are multiplied via AND gates, physically co-located with the arrays.

5. The resulting bit stream frequencies converge to the desired posterior probabilities.

This architecture maps the mathematical operations of Bayes’ theorem into physical computing primitives using the memristor arrays for storage and localized analog/digital hardware for arithmetic. The stochastic computing handles the multiplication and summation while minimizing data movement. The distributed nature of the computation allows implementing sophisticated Bayesian models efficiently.

Harabi’s prototype system demonstrated the potential for orders of magnitude improvements in energy efficiency compared to microprocessors. However, further optimizations in power could be made by using emerging devices like SOT-MRAMs for true random number generation rather than the LFSRs [53]. The binary architecture may also limit model accuracy compared to systems storing probabilities using multi-level memristors. While custom-designed for Bayesian processing, Harabi’s digital approach could face challenges in matching the raw computational throughput of some analog in-memory neural network accelerators. Overall, the work makes excellent progress in tailoring memristor architectures to the specific needs of probabilistic inference, though analog and hybrid schemes may provide further advantages.

2.4 Memristor as MCMC sampler

While Harabi’s work relied on stochastic computing, the implementation was rather complex and required complex electronics such as level shifters, and comparators. In a recent work Dalgaty et al. demonstrated a novel approach to utilize the intrinsic variability of memristive devices for machine learning [54]. Rather than viewing the cycle-to-cycle conductance fluctuations in devices like HfO_x Resistive Random Acces Memories (RRAMs) as a nuisance, the authors exploit it as a useful source of randomness. They configure a large RRAM array to physically realize a Bayesian machine learning model. The conductance states store the model parameters (likelihoods and priors) in a row-by-row fashion while the devices’ stochastic switching implements Markov chain Monte Carlo (MCMC) sampling for training and inference based on the previous state.

Specifically, The N × M memristor array with total 16,384 memristors is used to store and compute the posterior distribution for a Bayesian model with M parameters. Each row n stores one sample model ${\mathrm{g}}_{\mathrm{n}}$, with each of the M differential memristor pairs in that row encoding one parameter of ${\mathrm{g}}_{\mathrm{n}}$.

The posterior is computed iteratively row-by-row using MCMC sampling. At each step, row n contains the current sample model ${\mathrm{g}}_{\mathrm{n}}$. To generate the next sample model ${\mathrm{g}}_{\mathrm{n}+1}$ at row n + 1, the conductance of each memristor pair is updated by exploiting the stochastic switching of memristors. Applying a set voltage pulse samples a new conductance from a normal distribution centered at the current state. This randomly proposes a new model ${\mathrm{g}}_{\mathrm{p}}$ that is either accepted or rejected.

If rejected, the same update step is repeated to propose a new model, with a digital counter C_n for row n incremented to track rejections. This counter represents the contribution of ${\mathrm{g}}_{\mathrm{n}}$ to the posterior. After acceptance, the process advances to the next row. Over many rows, the distribution of stored conductance states converges to the target posterior distribution.

Despite memristor drift over 10 million switching cycles, the approach retains accuracy. Benchmarking indicates orders of magnitude efficiency gains over CMOS implementations of MCMC sampling with a typical energy consumption training being at 1 pJ per bit, with overall training expenditures being at 1–10 μJ whereas comparable task on consumer grade PC takes at most 1 J. By embracing rather than mitigating device non-idealities, this work opens a promising avenue for efficient in-situ Bayesian learning in memristive hardware.

2.5 Stochastic Bayesian computing with 2D materials

Previous examples show tremendous progress towards implementation of Bayesian machines. However, these approaches are based on conventional lithography techniques that frequently do not provide access to emerging materials and rapid prototyping techniques like printing for ultra-low power computing. Recently a materials science research group at Penn State University published two papers that descibes hardware implementation of Bayesian network using novel 2D memtransistors [55]. Similar to Harabi et al. [52] in this work, Bayesian networks in implementation was based on generating stochastic bits (s-bits) that randomly sample between 0 and 1 to represent probabilities.

The authors utilize monolayer molybdenum disulfide $\left({\mathrm{MoS}}_2\right)$ memtransistors, where cycle-to-cycle fluctuations in the programmed conductance state provide inherent stochasticity. They design a compact s-bit generator circuit comprising just six memtransistors that can tune the probability of 1’s in the bitstream from 0 to 1. This exploits the devices’ non-volatile yet analog programmability.

Integrating multiple s-bit generators with 2D memtransistor-based logic gates, they demonstrate a hardware architecture for Bayesian network nodes. The approach is applied to a simple two-node network, accurately estimating conditional probabilities. By computing directly in memory, the architecture is estimated to be extremely energy efficient at around 1 pJ per s-bit.

The key innovation is developing fully in-memory Bayesian computing leveraging emerging devices. Unlike prior works using two-terminal memristors or spintronics that rely heavily on CMOS peripherals, the three-terminal 2D memtransistors enable standalone stochastic logic. This could unlock new applications in edge intelligence and probabilistic computing. The demonstration of area- and energy-efficient uncertainty handling highlights the potential of co-designing algorithms and nanodevices.

The same lab also presented another work where they utilized a combination of monolayer ${\mathrm{MoS}}_2$ and ${\mathrm{WSe}}_2$ memtransistors, leveraging their analog programmability and cycle-to-cycle conductance fluctuations. A compact circuit comprising just two ${\mathrm{MoS}}_2$ memtransistors implements a stochastic synapse that can sample weights from configurable Gaussian distributions. Integrating ${\mathrm{MoS}}_2$ and ${\mathrm{WSe}}_2$ devices enabled modified tanh and sigmoid activation functions.

These synaptic and neuronal building blocks are then combined in a crossbar array architecture to physically implement BNN computations like a vector–matrix multiplication. The authors demonstrate a BNN circuit for disease classification using SPICE simulations. Uncertainty decomposition reveals the various entropy components.

Table 2 summarizes the differences of the works discussed in this chapter.

	Harabi et al.	Zhang et al.	Dalgaty et al.	Sebastian et al.
Architecture	Bayesian machine	BNN	BNN	BNN
Device technology	HfOx memristors	MoS2 memtransistors	HfOx memristors	MoS2, WSe2 memtransistors
Array size	16 × 8 × 8 (2048 devices)	6 memtransistors	16,384 devices	Not discussed
# of levels	Binary (LRS/HRS)	Analog	Binary (LRS/HRS)	Analog
Key mechanism	Binary conductance states and external CMOS stochastic blocks	Cycle-to-cycle variation for intrinsic stochasticity	Cycle-to-cycle variation for MCMC sampling	Analog conductance states and stochastic switching
Implementation	130 nm CMOS	Compact circuit demo	Computer-in-loop with memristor array	Crossbar BNN SPICE simulation
Training approach	In situ MCMC sampling	Pre-trained inference	In situ MCMC sampling	Pre-trained inference
Energy consumption	∼2 pJ/bit	∼2 pJ/bit	1 pJ/bit	18.37 nJ inference
Endurance	Not discussed	Not discussed	10 M cycles	Not discussed

Table 2.

Comparison of memristor/memtransistor based Bayesian computing approaches.

3. Conclusions

This work presented a range of toolkits for bio-inspired computing using memristors and neuristors, providing both original research and a literature review. In particular, we highlighted that memristors are versatile elements capable of storing information, performing computation in passive artificial neural networks, and being utilized in spiking neural networks and Bayesian machines. We demonstrated theoretically that passive memristors exhibit NDR when randomly connected in networks. Individual devices also show oscillatory properties, similar to an active neuristor, when cooling and heating at nanoscale are considered. Such oscillations could lead to spiking neural network implementations. In particular, a novel memristive device model exhibiting chaotic dynamics was introduced. The proposed model incorporates non-linear drift behavior based on the thermodynamic principles of Newtonian cooling and Joule heating within the memristive element. Numerical simulations demonstrate that this minimal model is capable of producing chaotic oscillations. The complex oscillatory characteristics and inherent stochasticity arising from the chaotic memristor suggest potential utility for hardware-based stochastic computing architectures. Further research is warranted to fully characterize the dynamical landscape and harness the rich nonlinear dynamics for unconventional computing paradigms.

Additionally, we explored an alternative approach of Bayesian computing with memristors. We reviewed some of the most recent works leveraging emerging memory technologies like memristors and memtransistors for efficient in-situ Bayesian inference. These approaches harness the intrinsic stochastic switching dynamics of such devices through either binary conductance fluctuations or analog variability. This avoids the need for expensive external CMOS random number generation and enables direct physical mapping of probabilistic models into memory arrays.

While these results are promising, memristor/memtransistor-based Bayesian computing remains in early development stages. Key near-term challenges to address include improving endurance, tolerance to variations, and energy efficiency. Integrating appropriate peripheral circuits for parallel readout and programming also needs to be solved before large-scale systems can be realized. Significant co-innovation across algorithms, circuit designs, and nanomaterials will be essential to unlock the full potential of in-memory Bayesian accelerators.

Longer-term research can explore hybrid CMOS-memristor architectures and systems integrating sensing, learning, and actuation for adaptive Bayesian edge intelligence. More complex Bayesian models like Bayesian neural networks and probabilistic deep learning equivalents should be mapped to further leverage emerging device properties. This co-design approach combining tailored algorithms, devices, and hardware for probabilistic inference may enable new ultra-low power intelligent systems for autonomous edge applications.

In conclusion, the intersection of Bayesian techniques and nanoscale memristive devices holds exciting promise to impart human-like uncertainty handling and adaptable intelligence to future electronics. Academic research leveraging their complementary strengths can establish the foundation for this next generation of probabilistic computing hardware.

Conflict of interest

The authors declare no conflict of interest.