Impact of Process Variations on the Performance of Wavelength-Dependent Devices

Abstract

One of the main factors for the rapid growth and industrialization of the integrated photonics field was the previous development by the microelectronics sector of lithography tools and processes for complementary metal oxide semiconductor fabrication, now also employed in the fabrication of photonic integrated circuits. However, the scarce range of methods to fine-tune photonic devices during the lithographic process results in a disparity between designed and manufactured devices. For the current state of lithographic resolution, when considering wavelength-dependent devices, such as Bragg gratings, this disparity can significantly alter the design of the component and impact its performance, as the response strongly depends on its geometry. Thus, understanding the impact of lithography in a photonic component is extremely important to minimize these variations and optimize the design process. This chapter explores the impact of manufacturing process variations, studying their effect on device geometry through a case study on contra-directional couplers, toward ultimately reducing the existing gap between designers and foundries.

1. Introduction

The main purpose of this chapter is to provide the reader, in particular one who is starting their endeavors in photonic integrated circuits, with the basic concepts of lithography and how this process may influence the experimental response of the designed devices by altering their geometry through a series of effects, ultimately leading to a variation of effective refractive index of the propagated mode. We hope to establish a coherent understanding of the different challenges faced in fabrication to obtain accuracy and reliability from die to die and from wafer to wafer, and assist in empowering designers by showcasing the distinctions between foundry-used terms and typical modus operandi. To showcase how the entirety of the process affects device’s responses, especially those that are wavelength dependent, we expose the issue through experimental data of contra-directional couplers (contra-DCs).

1.1 Lithography methods

Silicon-on-insulator (SOI) platforms have emerged as a promising technology in the field of photonics. Silicon photonics, while still in its early stages of development and commercialization, offers a number of advantages for manufacturing, namely the well-established industry of producing silicon wafers for microelectronics [1]. The integration of photonic devices onto silicon chips offers the advantages of energy efficiency, affordability, and high-volume production through the use of complementary metal oxide semiconductor (CMOS) fabrication techniques imported from the microelectronics sector [1].

Photonic integrated circuits (PICs) are commonly fabricated using electron-beam lithography (EBL) or deep-ultraviolet (DUV) lithography. In both methods, the initial step consists of depositing a photoresist on top of the silicon layer to be patterned. This photoresist will act as a protective layer for the silicon during the etching process. The workflow of the two lithography methods is depicted in Figure 1, and it can be noted that the only difference between them lies in the photoresist patterning.

Figure 1.

Workflow of the lithography process through E-beam lithography or DUV lithography.

1.1.1 Electron-beam lithography

EBL is a maskless lithography technique that uses the orientation of an electron-beam canon to imprint the intended design onto the resist [2, 3]. It is a direct writing method, meaning that each point is written in succession, so the design pattering is extremely slow and dependent on the chip footprint and density. It has several advantages such as reduced feature size and improved precision. However, its main drawback is its low production rate, which makes it unsuitable for large-scale fabrication [4]. Long structures that cross the wafer are also subject to stitching errors as a result of crossing multiple writing fields (typical writing field sizes are 100, 250, 500 μm, and 1 mm [5]), which can ultimately lead to device malfunction. As such, this technique is mainly used for research purposes to fabricate novel devices.

1.1.2 Deep-ultraviolet lithography

Contrary to EBL, DUV lithography is not a direct writing technique. It requires an intermediate step, where a chromium mask is patterned through either EBL or direct laser writing. However, once the photomask is acquired, it can be continuously used to produce chips. The photoresist layer is exposed using ultraviolet radiation, usually from UV lamps, with common wavelength values of 193 or 248 nm [6], that pass through the non-opaque features of the mask. This technique is known as projection printing because it uses a series of lenses to focus radiation onto the wafer. Compared to EBL, DUV lithography has a much bigger image field that may design an entire die in a single exposure in a few seconds. The whole wafer is patterned quickly as well with the assistance of a wafer stepper (a machine that advances the wafer to expose another portion that corresponds to a different die) [4, 7].

This fabrication technique is also the most common in CMOS manufacturing procedures. By borrowing this process, the PIC industry has the advantage of utilizing already implemented CMOS foundries, which leads to a considerable leap in the advancement of the technology compared to the primordial days of the CMOS industry [4].

The choice of which lithography process to opt for comes down to several factors. Table 1 presents the pros and cons of the two methods explored.

Lithography method	Pros	Cons
EBL	Better resolution	Slow writing rate
	Smaller feature sizes	Unsuitable for high-volume production
	Maskless process cost-effective for low-volume applications (e.g., investigation)
DUV	Large image field	Worse resolution
	Cost-effective for high-volume production	Larger feature sizes

Table 1.

Pros and cons of EBL and DUV lithography.

1.2 Lithography errors

Despite being an extensively researched and developed technique for microelectronics and, more recently, integrated silicon photonics, DUV lithography is still prone to errors. Since the response of photonic devices is often more dependent on the structure’s geometry than in the case of CMOS devices, it is critical to be aware of their potential impact.

1.2.1 Corner rounding

Corner rounding is the process of smoothing rectangular corners, which makes them less defined and more rounded. The photomask’s rounded corners or feature sizes approaching or surpassing the resolution limit are the causes of this impact [8]. The existence of rectangular shapes in the original design can be significantly impacted by this phenomenon. Consequently, rather than the desired rectangular shape, a square profile may exhibit a sinusoidal shape [9].

1.2.2 Line shortening

Line shortening reduces the width of waveguides and may potentially cause format changes. Due mostly to diffraction, chemical species diffusion in the resist, and fluctuations in the photomask pattern, this effect becomes increasingly substantial as feature sizes approach the resolution limit [10]. This issue can have an impact on diameters and waveguide widths of a photonic device.

1.2.3 Design deviation nonlinearity

Nonlinearity refers to the difference in printed feature sizes that do not match the intended dimension. The variation imposed is usually small and insignificant for large dimensions; however, as the feature size drops, the difference between the planned and printed dimensions becomes considerably more evident. This effect is particularly noticeable for dimensions that are closer to the resolution limit. Most severely, nonlinearity may prevent some features from being printed [10].

1.2.4 Proximity effect

When feature sizes are the same as, or very close to, the lithography system’s resolution limit, the proximity effect occurs, which is the variation of the dimensions printed onto the wafer as a result of environmental conditions, such as the close proximity of two waveguides. Due to their closeness, this effect causes fluctuations in the widths and distance between two close waveguides, and its significance increases as the spacing decreases [10]. This phenomenon can significantly affect the gap between two close waveguides; if the waveguides are subjected to slight fluctuations, the gap between them will subsequently change [4].

1.2.5 Sidewall roughness

In a rectangular waveguide, sidewall fluctuations arise from sidewall roughness. These fluctuations lead to slight changes in the waveguide’s width, which in turn affects the waveguide’s effective refractive index throughout its length [11]. This phenomenon may result in considerable phase error and propagation losses [12].

1.3 Foundry bias vs. fabrication variability

Two main causes of variability are usually present in the fabricated devices. The first one refers to the bias that is introduced by the specific foundry workflow. Foundries provide a Design Manual (a document containing the rules that designers must follow, and stack and layer information) with an interval of values in which this error is inserted. This type of variability is constant within the foundry runs for the same design and can be accounted for after the first iteration. Its source is the lack of in-line testing methods that enable the accurate measurement of the structures being designed, which, compared to CMOS devices, have a higher range of distinct geometric features, and cannot be easily tested in terms of functionality.

The other cause of variability lies in the errors discussed in Subsection 1.2 and the overall resolution and accuracy of the process that, all combined, contribute to the geometric and functional variance across the wafer of the designed structures. Unlike the foundry bias that can be predicted and accounted for in the design from wafer to wafer, fabrication variability is often “random” within the same wafer. Its values are low, in the order of few nanometers, and, for most structures, do not impact the functionality of the device. However, for structures that have features below the limits of resolution and are, therefore, more vulnerable to lithography errors, the geometric variability between dies (individualized sections of a wafer, repeated throughout it) increases. If that same device is wavelength dependent, with high contrast between the cladding and core refractive index, like in the case of SOI platforms, then this variance has a higher impact on the functionality of the device. That same impact will be presented and studied in Section 2.

1.4 Contra-directional couplers

A contra-DC is a device composed of two parallel waveguides in close proximity, each with periodic sidewall corrugations, combining the characteristics of a Bragg grating and a directional coupler forming a four-port device: in, through, drop, and add (Figure 2a).

Figure 2.

(a) Structure diagram and (b) typical simulated spectral response of a contra-DC.

Due to the corrugations in the waveguides, the optical signal traveling the device will experience partial reflections at every corrugation. As such, constructive interference will arise for wavelengths that satisfy the Bragg condition [13], as shown in Figure 2b. In the case of the contra-DC, this condition is expressed by:

$${\beta }_1+{\beta }_2=\frac{2\pi }{\mathrm{\Lambda }}$$E1

where $\mathrm{\Lambda }$ is the pitch of the corrugations and ${\beta }_{1,2}$ are the propagation constants of the waveguides given by:

$${\beta }_{1,2}=\frac{2\pi n_{\mathrm{eff}1,2}}{\lambda }$$E2

where $n_{\mathrm{eff}1,2}$ are the effective refractive indices of the waveguides and $\lambda$ is the wavelength of the propagated mode.

Contrary to a regular directional coupler designed specifically for power coupling, the waveguides of a contra-DC have different widths and, therefore, different propagation constants (expressed in Eq. (1)), thus reducing the forward-propagating co-directional power coupling between waveguides [1]. Because of this feature, only the backward-propagating mode (the signal reflected at the Bragg gratings) will couple into the second waveguide. Therefore, when a signal enters the device through the in port, the portion of the signal that satisfies the Bragg condition will thus exit at the drop port while the rest of the signal will exit at the through port.

Solving Eq. (1), we arrive at a simplified condition for the reflected wavelength in the case of contra-DCs:

$${\lambda }_{\text{Bragg}}=\left(n_{\mathrm{eff}1}+n_{\mathrm{eff}2}\right)\mathrm{\Lambda }$$E3

where ${\lambda }_{\text{Bragg}}$ is the Bragg wavelength, and $n_{\mathrm{eff}1}$ and $n_{\mathrm{eff}2}$ are the effective refractive indices of the first and second waveguides of the contra-DC, respectively.

As stated in Eq. (3), the central wavelength of the filtered response will depend only on the effective refractive indices of both waveguides and the pitch of the corrugations. However, for each individual waveguide, the Bragg condition for each grating can be satisfied, thus giving rise to intra-waveguide reflections. Analogously to Eq. (3), these reflected signals will have their central wavelength at ${\lambda }_1=2n_{\mathrm{eff}1}\mathrm{\Lambda }$ and ${\lambda }_2=2n_{\mathrm{eff}2}\mathrm{\Lambda }$, for the first and second waveguides, respectively. Because of this phenomenon, contra-DCs possess an anti-reflection design (already demonstrated in Figure 2a) that consists of the misalignment of the sidewalls that compose the Bragg gratings, phase-shifting them by 180° [1]. By misaligning the sidewalls, the signal now reflects with a $\pi$ shift from sidewall to sidewall, thus making the partial reflections interfere destructively. As a result, the signals at ${\lambda }_1$ and ${\lambda }_2$ are no longer reflected to the drop port, ultimately removing undesired peaks from the spectral response of the contra-DC [14].

This device has been extensively studied by the SIEPIC group from the University of British Columbia in Canada, led by Professor Lukas Chrostowski [1, 15, 16]. They have put forward multiple tools to assist in photonic integrated circuit design available to the public, including a repository containing scripts for simulating a contra-DC using Ansys Lumerical [17], present in Appendix A, by Mustafa Hammood. Additionally to their contributions, we also leave a code of a parameterizable contra-DC in GDS Factory [18] for implementation of this building block in future designs in Appendix B.

2. Impact of geometry variations on photonic devices: a case study on contra-DCs

In photonics, SOI platforms are most commonly used, given the advantageous property of high-confinement waveguides [1], due to the high contrast of refractive indices of Si that compose the waveguides and SiO₂ that compose the cladding. However, this high contrast also translates into large variations of effective refractive index when the geometry of the waveguide alters.

To evaluate the effect in the optical properties of integrated waveguides on photonic structures that their geometry imposes, a study on Ansys Lumerical MODE solver [17] was performed on an SOI platform with a sidewall angle of 85, considered to approximate the design to the as-fabricated waveguide.

Figure 3 shows the variation of effective refractive index ($n_{\mathrm{eff}}$) of a waveguide with the variation of its width, for a thickness of 220 nm.

Figure 3.

Variation of effective refractive index of a Si waveguide as a function of its width.

The impact that varying the width of a waveguide has on its $n_{\mathrm{eff}}$ is clearly visible. With an approximately linear variation of effective index, when one considers a Bragg device along with its phase condition, it becomes clear that if the waveguide width deviates from the designed width, so will the Bragg wavelength of the grating, which may greatly impact the performance of the device.

Figure 4 is an image taken with scanning electron microscopy (SEM) of a section of a contra-DC that was fabricated through DUV lithography. It is possible to observe a significant rounding of the corrugations whose shape becomes sinusoidal with the lithography effect. This over-etch will be responsible for a significant decrease in the bandwidth due to the increase of the gap between waveguides and the erosion of the corrugation width. It will also be responsible for a shift in the central wavelength of the contra-DCs, by the phenomenon just analyzed in Figure 3. Since the corrugations are created by a shift in the position of each half-period section instead of by variations of widths as part of the anti-reflection design, the effect of lithography onto the waveguide width of the corrugations section can be approximately correlated to the shift in central wavelength.

Figure 4.

SEM image of a contra-DC section.

With these results in mind, three wafers with contra-DCs fabricated through DUV lithography were characterized, and a model that relates the geometry of the waveguides with the measured optical properties of the contra-DCs was conceived and explored, which will be the focus of the next section.

2.1 Die-to-die study

To study the variation and impact of the lithography process on wavelength-dependent devices, a SOI wafer containing 72 dies with contra-DCs, fabricated through 193 nm DUV lithography, was fully characterized. The optical spectra at the drop and through ports were acquired and analyzed.

The central wavelength of the drop response of each contra-DC was mapped according to its position on the wafer. Figure 5a shows the central wavelength map of the wafer, where the scale is shown as the difference between the expected central wavelength from the design (${\lambda }_{\mathit{\text{designed}}}$), which was obtained through simulation beforehand, and the measured central wavelength of the devices (${\lambda }_{\mathit{\text{measured}}}$).

Figure 5.

Central wavelength map of (a) full wafer and (b) wafer without outer ring PICs (represented in gray).

From Figure 5a, we can see the clear variation of central wavelength present across the wafer. The maximum redshift obtained was 26.1 nm while the maximum blueshift was −9.5 nm. Furthermore, the average difference between expected and measured central wavelength is 0.05 nm while the standard deviation is 7.7 nm.

Despite the seemingly small difference between average measured central wavelength and expected central wavelength, observing Figure 5a, it is visible that the redshift of the outer ring dies (contra-DCs at the edge of the wafer) is what is causing this effect while the center of the wafer seems to be predominantly blueshifted. Furthermore, it is noticeable that the outer ring of the wafer follows a much more random variation than the ones located toward the center of the wafer. This phenomenon is associated with a particular step of the fabrication process; the photoresist that is deposited on top of the Silicon layer is done so through spin coating. This technique consists of dispensing the fluid in the center of the wafer while it spins at several thousand rotations per minute. The centrifugal force associated with the rotation movement creates a laminar flow of the fluid toward the edge of the wafer, creating a uniform thin film. However, due to the surface tension at the borders, the fluid tends to accumulate at the edges of the wafer, thus making the thickness of the layer in these regions usually greater [19].

Due to the thicker layer of photoresist at the edges of the wafer, when it is exposed to UV radiation, the photonic design is not etched as well as in the center region of the wafer. Because of this phenomenon, devices fabricated at the edge of wafers are commonly discarded [19].

Taking this account, the wafer without the outer ring was analyzed; the central wavelength map of the wafer is shown in Figure 5b, where the variation is notably less significant. Without the edge dies (represented in the figure in gray), the average difference of central wavelength becomes −4.2 nm with a significantly smaller standard deviation of 2.0 nm. Comparing these results to the full wafer analysis, we can conclude that the tendency is for the devices to be blueshifted from what was designed.

Furthermore, it is possible to determine that, contrary to the edge of the wafer, the remaining dies follow a more consistent shift from the expected value, which leads to the conclusion that the majority of the inner dies suffer mostly from foundry bias.

It should be noted that the devices characterized in this work were not the result of the first run with the foundry, and, as such, the designs already possessed a compensation factor that was induced from previous runs done with the same foundry. For this reason, the devices present a smaller central wavelength shift than usual first-run devices.

2.2 Wafer-to-wafer study

Following the die-to-die analysis presented previously, it was important to assess the variability of the performance of the devices across multiple wafers, in order to better understand the origin of the wavelength shift of the contra-DCs (as explored in Section 1.3) and evaluate the reproducibility of the results.

Dies from two additional identical wafers were characterized and analyzed, with 19 samples each. It is important to note that only dies from the inner region of the wafer were included in this analysis as a consequence of the study and conclusions presented in Section 2.1.

Figure 6 shows the results for all three wafers regarding the central wavelength of the contra-DCs, as well as the average of the three wafers for each die. In Table 2, the average and standard deviation of each wafer are displayed. Once again, all results are presented relative to the expected results (${\lambda }_{\mathit{\text{measured}}}-{\lambda }_{\mathit{\text{designed}}}$).

Figure 6.

Central wavelength map of (a) wafer A, (b) wafer B, (c) wafer C, and (d) wafers’ average (the points present in the graphs of this figure are solely the common dies tested among all wafers to assure accuracy in the statistical analysis).

Wafer	Average	Standard deviation
	${\lambda }_{\mathit{\text{measured}}}-{\lambda }_{\mathit{\text{designed}}}$ (nm)	${\lambda }_{\mathit{\text{measured}}}-{\lambda }_{\mathit{\text{designed}}}$ (nm)
A	−4.4	1.9
B	−5.0	1.6
C	−5.3	2.6
Overall	−4.9	1.9

Table 2.

Central wavelength performance for all wafers.

From Table 2, it is clear that the shift observed in the contra-DCs is similar across all three wafers tested, with the average central wavelength of the wafers varying within less than 1 nm. Consequently, the hypothesis that the main impact is the foundry bias gains more strength. This translates into a constant difference in waveguide width from designed to fabricated, which will be explored further.

Analyzing the overall result, which is the average of the three wafers that were characterized, the central wavelength is, on average, blueshifted by 4.9 nm from the expected; this implies that, on future runs, if this figure of merit is compensated, the devices will expectedly be closer to the desired performance. Taking the foundry bias into account, the central wavelength shift can be related to the waveguide width of the devices, which can be extracted, accounted for, and corrected in future designs, provided they are manufactured in the same foundry. This study will be the focus of the next section.

2.3 Geometry extraction model

In integrated wavelength-dependent devices, such as contra-DCs, the source of performance deviations is geometry variations induced by the fabrication process. Therefore, it is of the utmost importance to relate these two elements in a way to optimize future designs.

Based on the laboratory results presented in Sections 2.1 and 2.2, a model relating the central wavelength of the optical response measured from a contra-DC and the waveguide width was developed. For the following analysis, the impact of the variation in thickness in the device’s response was not accounted for.

Recalling Eq. (3), the central wavelength of a contra-DC can be determined by plotting the respective dispersion curve of the Fundamental transverse electric (TE) mode (where $n_{\mathrm{eff}}=\frac{n_{\mathrm{eff}1}+n_{\mathrm{eff}2}}{2}$) and the Bragg condition ($\frac{\lambda }{2\mathrm{\Lambda }}$). The intersection point between the two curves will be the theoretical central wavelength of the device.

Dispersion curves for contra-DCs with different waveguide widths were obtained for widths of $w_{1,2}=400$, 300 nm to $w_{1,2}=500$, 400 nm. In this study, the waveguide width of the second waveguide was always considered to be 100 nm narrower than the first waveguide (e.g., $w_1=500$ nm, $w_2=400$ nm).

The results obtained are shown in Figure 7a. It is clear that the effective refractive index of the device increases as the waveguides widen due to the higher influence of the Si refractive index in the medium. Figure 7b presents the intersection points for each dispersion curve, which directly relates to the corresponding waveguide width. Therefore, from a measured optical response, one can directly extract the waveguide widths of the device through this curve.

Figure 7.

(a) Dispersion curves for different waveguide widths and effect on Bragg condition match and (b) waveguide width and Bragg wavelength relation.

Using the correlation established and represented in Figure 7b, the waveguide width of each device on wafer A (from Section 2.1) was extracted. The outer ring of the wafer was once again discarded. The results can be observed in Figure 8 and are presented as the difference between extracted width and designed width ($w_{\mathit{\text{extracted}}}-w_{\mathit{\text{designed}}}$).

Figure 8.

Waveguide width map of wafer A.

The variation of waveguide width follows the same pattern across the wafer as the central wavelength, as expected, since the waveguide width has a nearly linear dependency on the central wavelength (Figure 7b). All devices present smaller waveguide widths than the designed, with the maximum shift being −10 nm, while the average $w_{\mathit{\text{extracted}}}-w_{\mathit{\text{designed}}}$ is of −5.7 nm.

The waveguide width map was also extracted for the other wafers tested to establish a comparison between them. Figure 9 presents the results obtained for the three wafers as well as the overall average among wafers. Once again, it is observed that all devices from all wafers present a smaller waveguide width than designed. Furthermore, the three wafers seem to present the same map pattern (small deviation in die comparison between wafers), which indicates repeatability across wafers.

Figure 9.

Waveguide width map of (a) wafer A, (b) wafer B, (c) wafer C, and (d) wafers’ average.

As such, for future designs, two approaches can be considered: for a full wafer (private run) production, the designer may take the zone of the wafer where the device will be located into consideration for a more precise waveguide width compensation by using the precise value of the die average. Alternatively, considering a multi-project wafer (MPW) approach where the designer does not have access to the wafer region of its PIC, compensating the designs with the average of the wafer, thus increasing 6 nm in the waveguide width, would be the solution.

Despite these promising results that would minimize the wavelength shifts observed in future runs, one can also clearly see the variation from die-to-die and wafer-to-wafer, which cannot be attributed solely to foundry bias. These variations are related to the fabrication problems explored in Section 1.2. Contrary to the foundry bias-induced shift, these deviations are much harder to compensate given their randomness. Consequently, there is a limit to what the designer can do to eliminate this source of variability, and can therefore mostly take mitigation action at best, which will be the topic of the next section (Table 3).

Wafer	Average	Standard deviation
	$w_{\mathit{\text{extracted}}}-w_{\mathit{\text{designed}}}$ (nm)	$w_{\mathit{\text{extracted}}}-w_{\mathit{\text{designed}}}$ (nm)
A	−5.7	1.6
B	−6.0	1.4
C	−6.4	2.5
Overall	−6.0	1.7

Table 3.

Extracted waveguide width for all wafers.

3. Mitigation strategies

3.1 Fabrication

It is clear that the improvement of the lithography techniques leading to an increment of resolution would undoubtedly help to mitigate the fabrication errors that most PIC designers struggle with. Indeed, there have been advancements in lithography technology, and high-numerical aperture (NA) extreme ultraviolet (EUV) lithography technology with resolutions up to 13 nm is now a potential reality in the CMOS industry [20]. As the progress in lithography technology advances, the integrated photonics industry will also benefit from it.

As for the individual process of each foundry, in-line testing needs to become a reality to increase the reliability and reproducibility of the devices [21]. Morphological testing and critical dimension (CD) alignment are great improvement steps toward eliminating foundry bias. However, morphological testing requires the stopping of the process, which can significantly increase the fabrication time, while the CD alignment is only a viable solution for wafers with a similar layout among dies in terms of density.

Besides morphological testing, vertical grating couplers make functional testing at a wafer level possible, similar to a multi-probe station. But for novel structures, there will be a gap between the designer and fabrication engineer regarding the response of the device, especially if it is influenced by multiple parameters. The increase in the amount of structures present in each foundry’s process design kit (PDK), as a result of intensive testing and fabrication correction, will ultimately allow the increase of the accuracy of the design’s response, while simultaneously increasing the designer’s possibilities.

3.2 Lithography simulators

Meanwhile, designers and foundries can and should collaborate to create and improve lithography simulators, which are simulation programs that allow the emulation of the effect that lithography will have on the features designed. This type of tool is crucial for developing devices that contain features with dimensions below the resolution’s limits. Currently, multiple simulation companies such as Synopsys and Siemens have their own solutions (Synopsys S-Litho and Siemens Calibre) that were developed for the IC industry but that the PIC industry can also benefit from. Apart from commercial simulators, there are several open-source solutions, such as PreFab Photonics [22] and ELIAS from the University of Texas at Austin [23]. Open source or not, the main set-back present in these programs is their requirements of either lithography model parameters, such as $\mathit{NA}$ (related to the ability of the lens to collect light; range of the angular acceptance of the lens), $\sigma$ (partial coherence factor; a measure of the angular range of the illumination relative to the angular acceptance of the lens) and $\mathit{\delta \sigma }$ (angular variation ranges from which the intensity of the optical beam rises from 0.5% to 99.5%) [4, 7] which would require in-depth knowledge of the foundry process, and therefore are not accessible to fabless designers, or of a sample of SEM images of test structures from the foundry and process of interest, typically not supplied in MPWs [4, 22].

3.2.1 PreFab photonics emulation of a contra-DC

We used PreFab Photonics [22] as an experimental lithography simulator to observe the prediction of the impact of fabrication on a contra-DC. The only models available at the time were from Applied Nanotools Inc., which exclusively fabricates with EBL; therefore, we are not able to draw extensive conclusions, given that our devices were fabricated through DUV lithography. As expected, the corrugations of the device are the most affected, given that they fall below the resolution limit. But as seen in Figure 10, the corner rounding effects in the corrugations are even more severe, leading to a sinusoidal shape of the waveguide edges. This will clearly impact the central wavelength, given that the width will decrease due to the over-etch of the corrugations. The period has remained identical, so it is possible to consider the waveguide width as the main factor of the central wavelength variation.

Figure 10.

(a) Input design in the PreFab Photonics lithography emulator and (b) lithography simulation of the input design using the ANT NanoSOI v3 model.

3.3 Design as a lithography error mitigation strategy

Ultimately, all the strategies presented above are limited in mitigating the lithography variability. For devices where the variation in the structure dimensions will almost equally impact the response’s central wavelength, such as in the case of the contra-DCs, designing needs to be included as a strategy to mitigate error. The clearest answer would be to limit the use of structures that do not push or are as not as affected by the resolution limits. However, for the cases where that is not possible, we present two solutions.

3.3.1 Device tuning

Tuning refers to the method of slightly varying the response of a device by modeling the refractive index of the material (clearly leading to a variation in the effective refractive index of the propagated mode) through the change or exposure of a physical property most often represented by a constant, such as temperature (thermo-optic coefficient) or an electric field (Pockels coefficient). Regarding contra-DCs, it has been reported that 80 K would be necessary to reach a variation of central wavelength in SOI slightly higher than 5 nm [24], which renders the strategy inefficient, given the high-power consumption that the PIC would require. Wei Shi, et al. reported a 7 nm shift in wavelength with 18 V applied to a Contra-DC designed in a rib platform with a p-i-n structure for high-speed tuning or switching through carrier injection [25].

3.3.2 Designing for redundancy

Designing for redundancy means multiplying the critical components present in our circuit to enhance reliability and availability. By having several contra-DCs in place with slight parameter variations, the probability that one of them will give the pretended response is higher than to just employ a single device. This strategy would require the employment of photonic switches, allowing the system to tolerate the failure of one structure without compromising its overall functionality. However, this approach will lead to a chip with a bigger footprint and increased complexity.

4. Conclusions

In this chapter, the impact of the lithographic process on PICs and, most importantly, in wavelength-dependent devices was explored. A case study on contra-DCs was developed, and the performance of the devices, according to their position in the wafer, was studied and analyzed.

Through this case study, we found that devices located on the outer ring (at the edge) of the wafer present a significant central wavelength deviation when compared to identical devices that were fabricated toward the center of the wafer. These findings lead to the conclusion that devices manufactured in these regions of the wafer are not viable, as they tend to present a random and large performance deviation.

Excluding the contra-DCs from the wafer’s edges, we observed a systematic deviation among devices when comparing them die to die and wafer to wafer, with an average of −4.9 nm between measured and expected central wavelength and a standard deviation of 1.9 nm. The results indicate the predominance of a foundry bias in the fabrication process of the characterized wafers.

In view of the characterization results obtained, a geometry extraction model was created in order to directly relate the optical response of the contra-DCs and their waveguide widths. Through this model, it was possible to induce the value of the foundry bias of the wafers in study, where the extracted widths of the devices are, on average, 6.0 nm narrower than the designed waveguides.

Regarding the variability present in the dies, foundry bias was found to be predominant. This type of variability can be decreased further by adjusting the designs according to the experimental values of each run. However, random variation is still present, as can be concluded by the value of standard deviation. Although it contributes with a much smaller value to the variability of the devices, since it is tied to the limits of resolution and present lithography errors, it will always remain an unpredictable hindrance to designers.

Overall, the study allows for a sense of the existing gap between designers and foundries. Although developments have been made regarding lithography fabrication tools that further push the limits of resolutions, with techniques such as EUV lithography, those are still hard to access. Therefore, designers must focus on solutions that allow the control or contour of the fabrication effects, such as the implementation of tuning or designing for redundancy. Increasing foundry testing of structures through morphological or functional verification should lead to optical responses of higher accuracy. The challenge is implementing them with no further significant strain during the fabrication process.

Acknowledgments

This work is supported by the European Regional Development Fund (FEDER), through the Competitiveness and Internationalization Operational Programme (COMPETE 2020) of the Portugal 2020 framework [Project POWER with Nr. 070365 (POCI-01-0247-FEDER-070365)].

Appendix A

SIEPIC contra-DC simulator repository by Mustafa Hammood: https://github.com/SiEPIC/contraDC.

Appendix B

Nomenclature

CD	critical dimension
CMOS	complementary metal oxide semiconductor
contra-DC	contra-directional coupler
DUV	deep-ultraviolet
NA	numerical aperture
EBL	electron-beam lithography
EUV	extreme ultraviolet
IC	integrated circuit
MPW	multi-project wafer
PDK	process design kit
PIC	photonic integrated circuit
SEM	scanning electron microscopy
SOI	silicon-on-insulator
TE	transverse electric