Floating-Point Arithmetic with Consistent Rounding on a Quantum Computer

Abstract

Implementation of floating-point arithmetic with consistent rounding is a critical component of many quantum algorithms. Quantum circuit implementations for squaring and division serve as examples here. This work was motivated by ongoing work in developing quantum algorithms for scientific and engineering computing applications, where this type of arithmetic often forms part of the algorithm. A key feature of the work is the use of a reduced-precision floating-point representation of real data specifically designed for near-term future quantum computing hardware with a limited number of qubits (e.g., less than 100) and with an increased level of fault tolerance as compared to current quantum computing hardware. The quantum circuit implementations of the squaring of a floating-point number and the division of two floating-point numbers are detailed here, highlighting similarities in the quantum circuit implementation for the logical steps required for rounding-to-nearest in line with the IEEE 754 standard for the two arithmetic operations. This similarity is an important feature regarding future work where an automated generation of this type of quantum circuit from a set of standard modules and circuit templates is employed.

1. Introduction

In quantum computing [1] research, significant progress is being made in developing quantum information processing hardware. This has so far created prototype quantum computers in research centers, as well as small-scale quantum computers accessible through the cloud to a wider audience. The current machines belong to the Noisy Intermediate Scale Quantum (NISQ)-computing era [2], characterized by the presence of a small number of qubits (typically less than 100) with significant sensitivity to noise and quantum decoherence and very limited quantum error correction. The ongoing quantum hardware development efforts create quantum computers with an ever-increasing number of qubits and increasing levels of fault tolerance.

The context of the present work is the ongoing development effort in creating quantum algorithms for computational science and engineering applications implemented using the quantum circuit model on future, more fault-tolerant quantum computers. In this type of quantum algorithm, there is often a need to perform arithmetic operations on real (non-integer) numbers within the quantum circuit-based implementation. In the quantum computing (QC) literature, there is a significant body of work on quantum circuit implementation for integer arithmetic [3, 4, 5], which can be re-used in fixed-point representations of real numbers. However, from the history of computing on classical hardware, it is clear that for most applications, a floating-point representation of data is more effective. Once floating-point numerical computation on classical computers became commonplace, the industry standard IEEE 754 was introduced [6]. A key feature of the IEEE standard is that it requires correctly rounded operations, including the correctly rounded arithmetic operations considered here. Typically, rounding to the nearest floating-pointing number available in the destination (output register) is used. A similar standard for floating-point representations on a quantum computer does not yet exist, but is desirable [7].

Recently, a small number of works have focused on quantum algorithms with a floating-point type representation of data. These works include research on floating-point arithmetic [8, 9, 10, 11, 12, 13] as well as research on data encoding and representation of quantum images [14, 15].

The present work discusses quantum circuit implementations for two example calculations typically found in computational science and engineering applications: evaluating the square of floating-point numbers (e.g., as part of kinetic energy evaluation) and the division of two floating-point numbers.

The quantum algorithms of interest here often involve the discretization and solution of partial differential equations (PDEs) that govern the conservation of physical quantities such as mass, momentum and energy. Therefore, it is important to have a consistent rounding in the arithmetic operations to avoid compromising the conservation properties of the discretization and solution methods. Rounding to the nearest floating-point number in the output register of an arithmetic operation is the preferred rounding mode in the context of computational science and engineering applications.

The key contributions of this work can be summarized as follows:

• Demonstration of a quantum circuit implementation of floating-point squaring with detailed analysis of how rounding-to-nearest can be achieved;

• Demonstration and analysis of quantum circuit implementation of floating-point division with rounding-to-nearest;

• Detailed discussion of the modular structure and similarities of the quantum circuit implementation of rounding-to-nearest for both arithmetic operations;

• Discussion of prospects for a wider range of quantum floating-point arithmetic.

The rest of this work is organized as follows. Following the review of related work in Section 2, Section 3 briefly reviews and summarizes key QC principles. Then, the floating-point representation used in the quantum circuit implementations is defined in Section 4. Section 5 discusses the quantum circuit implementation of the squaring of a floating-point number. Quantum circuit implementations for floating-point division are detailed in Section 6. Finally, Section 7 summarizes key findings and directions for future work.

2. Brief review of related work

An early work related to quantum circuits for floating-point arithmetic involved the complexity analysis of floating-point addition and multiplication by Häner and co-workers [8], which showed the significant challenges involved in terms of circuit complexity for IEEE-754 type precision. This motivated the present author to introduce floating-point formats for quantum algorithms with a reduced precision [12, 16, 17], such that the required number of qubits and the circuit complexity remain within limits of near-future quantum computers with an increased level of fault tolerance as compared to NISQ-era hardware.

Optimized circuits for floating-point addition and multiplication were detailed by Gayathri et al. [9] with a particular focus on minimizing the number of T-gates [1] in the implementation. The T-count optimized implementation for single-precision floating-point division was also investigated [10]. An efficient quantum circuit implementation for taking the square root of a floating-point number was detailed more recently [11]. In that work, the classical Babylonian algorithm was implemented using circuits for integer division.

Although the previously referenced works detailed key steps in quantum circuit implementations for floating-point arithmetic, the aspect of rounding was not addressed in detail. This formed the main motivation for the present work.

Key challenges in developing quantum circuit implementations for a divider are the reversibility requirement and fault tolerance, as analyzed by Babu and Mia [18]. The fault-tolerance aspect of a quantum circuit implementation of a floating-point divider was recently addressed by Yuan and their colleagues [13]. Implementations of dividers based on the long division approach perform a series of controlled subtractions for which a comparison operation between two integers encoded by qubit strings is required. Efficient quantum circuit implementations of such “comparator” circuits were published by Xia et al. [19]. Highlighting further recent research work related to quantum floating-point arithmetic, the work by Orts et al. [20] shows efficient circuit implementations for detecting the leading zero in a bit string, and operation typically required in subtraction, division, and multiplication operations.

3. Quantum computing essentials

In this section, some key concepts of quantum computing are reviewed. A full treatment can be found in many textbooks, for example, [1]. In the present work, the quantum circuit model is used to represent quantum algorithms, where a series of quantum gate operations act on a quantum state defined by a qubit register with $n$ qubits in a coherent state. Figure 1 shows two example quantum circuits with three qubits ($a$, $b$, and $c$) with three successive quantum gate operations. Dirac’s bra-ket notation is used so that the quantum state defined by a single qubit can be defined as $\mid q⟩=a\mid 0⟩+b\mid 1⟩$, such that ${\left|a\right|}^2$ is the probability of finding the qubit in state $\mid 0⟩$ when quantum measurement is performed, and ${\left|b\right|}^2$ is the probability of finding the qubit in state $\mid 1⟩$. Since a quantum measurement is guaranteed to return one of the two states, it follows that ${\left|a\right|}^2+{\left|b\right|}^2=1$. For a quantum state defined by $n$ qubits in a coherent state, we can write $\mid q_{n-1}\mid q_{n-2}\mid \dots \mid q_1\mid q0⟩={\sum }_{i=1}^{2^n-1}{C}_i$, where the $2^n$ complex amplitudes $C_i$ ($i\in \left[0,2^n-1\right]$) define the state. Often, the indices are expanded in binary representation to define the $2^n$ computational basis states.

Figure 1.

Definition of $\mathit{MAJ}$ and $\mathit{UMA}$ operations consisting of three gate operations, as used in Cuccaro-type adders.

In quantum circuit diagrams used in this work, each of the qubits is represented by a horizontal solid line, with a vertical arrangement of the multiple qubits in the register. Quantum gates either work on a single qubit (“single-qubit gates”) or work on multiple qubits (“multi-qubit gates”). The quantum computation progresses step-by-step in the horizontal direction, starting from the initial qubit register state defined on the left-hand side of the quantum circuit diagram.

The two example quantum circuits shown in Figure 1 are the building blocks of quantum arithmetic circuits to be discussed later. On the left-hand side of Figure 1, first a controlled $X$ gate is applied. This two-qubit gate applies the $X$-gate (the quantum computing equivalent of $\mathit{\text{NOT}}$ in classical circuits) to qubit $\mid b⟩$ conditional on qubit $\mid a⟩=\mid 1⟩$. Applying $X$ changes $\mid 1⟩$ to $\mid 0⟩$ or $\mid 0⟩$ to $\mid 1⟩$. Then, a second controlled-$X$ is applied, now with qubit $\mid c⟩$ as the target qubit. Finally, a Toffoli three-qubit gate is applied. This Toffoli gate applies $X$ to the target qubit ($\mid a⟩$ here) conditionally on the state of two control qubits. In the rest of this work, “multiply-controlled” versions of the Toffoli gate are used in the quantum circuit diagrams with more than two control qubits.

It should be noted that on actual quantum computing hardware, only a small hardware-specific set of gate operations (“native gates”) are implemented. The quantum circuit diagrams used in the present work therefore define algorithms at a higher level of abstraction, and in case of hardware realization, a further translation step toward native gates would be required.

Since a quantum circuit is composed of unitary operations [1], every quantum circuit has an inverse. The inverse of a quantum circuit can simply be composed of the inverse of all its constituent quantum gates, applied in reverse order. Here, it can be noted that the $\mathit{UMA}$ circuit shown on the right-hand side of Figure 1 is not the inverse of the operations from the $\mathit{MAJ}$ operation, since the final controlled-$X$ in $\mathit{UMA}$ is different from the first controlled-$X$ in the $\mathit{MAJ}$ operator.

In the present work, the concept of applying the inverse of an operation defined by a set of quantum gate operations is typically used as uncomputation, aimed at returning qubit states to their original state. This is typically used to return qubits allocated to create workspace to their initial state so that these can be re-used in subsequent parts of the circuit.

The quantum circuit implementation of the floating-point dividers considered here is based on modular quantum adders originally introduced by Cuccaro [4]. Figure 2 shows the example of a 3-qubit full adder, such that an integer “a” defined in 3-bit binary representation as $a2a1a0$ (with $a2$ and $a0$ representing the most significant bit and least-significant bit in the binary representation, respectively) is added to integer “b” (represented as $b2b1b0$ in binary representation). The Cuccaro full adder stores the result in the “b” input. For a full adder, an additional bit is therefore needed for the “b” register to ensure that the output can be represented. The qubit registers $\mid a2\mid a1\mid a0⟩$ and $\mid b3\mid b2\mid b1\mid b0⟩$ correspond to the corresponding bits of “a” and “b.” Their initial state on the left-hand side of Figure 2 defines the intended addition. Upon completion, the quantum state on the right-hand side of the circuit represents the output. The changed state of qubits $\mid b3\mid b2\mid b1\mid b0⟩$ relative to that at initialization represents the computational work performed. In later sections, modulo adders will also be used. For the Cuccaro-type adders used here, the underlying idea is that modulo adder can be obtained from the full adder by removing the controlled-$X$ operation in between the top $\mathit{MAJ}$ and $\mathit{UMA}$ blocks. The second modification involves not using the additional qubit on the “b” register, since by definition it is not needed for a modulo addition. The $\mathit{MAJ}$ and $\mathit{UMA}$ blocks act on three qubits and were previously defined in Figure 1. Furthermore, the quantum circuit implementation includes a “carry” qubit $\mid c⟩$, initialized as $\mid 0⟩$ in the applications considered here. A 3-qubit modulo adder can be obtained from the full-adder circuit shown in Figure 2 by removing the qubit $\mid b3⟩$ and the controlled $X$ operation between the $\mathit{MAJ}$ and $\mathit{UMA}$ blocks at the top of the circuit. Also, using the concept of 2’s complement representation of integer numbers, modulo adder can be used to perform subtraction operations.

Figure 2.

Illustration of Cuccaro-type full addition. Three-bit integer defined by $\mid a2\mid a1\mid a0⟩$ is added to integer defined by $\mid b3\mid b2\mid b1\mid b0⟩$ with the result stored in $\mid b3\mid b2\mid b1\mid b0⟩$.

4. Floating-point representation in quantum circuits

In previous work, the author introduced a floating-point representation with reduced precision relative to the IEEE-754 single-precision format [12]. A key motivation was the capability to represent a much wider range of real numbers as compared to a fixed-point representation when using the same number of qubits. In this floating-point format, a base $2$ representation is used, so that a non-zero, signed real number $y$ is represented in normalized form as:

$$y=\pm \mathit{SIG}\times 2^{\mathit{EXP}},\text{where}1\le S<2$$E1

where the numbers $\mathit{SIG}$ and $\mathit{EXP}$ are the mantissa (or significant) and the exponent, respectively. The standard convention for floating-point representations is followed here. $\mathit{SIG}$ is defined in a binary fixed-point representation such that the most significant bit is followed by the binary point and the fractional part to the right of this point [6]. The mantissa is defined using $M$ bits in a binary representation as,

$$\mathit{SIG}={\left(m_{M-1}.m_{M-2}\dots m_1{m}_0\right)}_2$$E2

Excluding the special cases involving sub-normal numbers and overflow conditions (to be detailed later), it is assumed that the most significant bit in the binary representation of $\mathit{SIG}$ equals 1. Floating-point numbers so defined are termed normalized [6]. Eq. (1) shows that normalized numbers cannot exactly represent the real value of zero. To account for this shortcoming and to better represent the smallest numbers in the range of numbers covered by the floating-point representation, sub-normal numbers are employed. Specifically, for the smallest value of $2^{\mathit{EXP}}$ in Eq. (1) used in the representation, an additional set of numbers is defined for which the most significant bit in $\mathit{SIG}$ equals $0$. In the floating-point representation, setting all bits used to define the exponent in binary to $0$ (i.e., $00\dots 00$) makes the number a sub-normal number. The value for $\mathit{EXP}$ used is identical to that used for the smallest of the normalized numbers, that is, with exponents defined as $00\dots 01$ in binary representation. Following the IEEE-754 floating-point formats, the exponent bits are also used to identify cases where overflow has occurred in the considered arithmetic operations, that is, where the real value to store does not fit within the range of numbers covered by the floating-point representation. In that case, all exponent bits are set to $1$, that is, the exponent is defined as $11\dots 11$. More details on using this approach for the IEEE-754 format can be found in standard textbooks, for example, Overton’s book [6]. In the quantum circuit implementation, a sign qubit is used which is in state $\mid 0⟩$ for a positive number. A negative number has this sign qubit in state $\mid 1⟩$. Following the “hidden-bit” approach used in the IEEE-754 standard [6], the most significant bit is not stored and $M-1$ qubits are used here to store only the fractional part of the mantissa. The exponent is defined using $E$ bits in a binary representation as,

$$\mathit{EXP}={\left(e_{E-1}{e}_{E-2}\dots e_1{e}_0\right)}_2-{\mathit{EXP}}_{\mathit{\text{bias}}}$$E3

where ${\mathit{EXP}}_{\mathit{\text{bias}}}$ is the exponent bias. In this work, $3$ qubits are used in the definition of the exponent $\left(E=3\right)$, contrasting with the $8$ bits used in the IEEE-754 single-precision format. For $E=3$, sub-normal numbers are defined by the exponent qubit string in state $\mid 000⟩$. Similarly, the exponent qubit string in state $\mid 111⟩$ represents overflow conditions. Also, the quantum circuit implementations are detailed for $M=4$, so that $3$ qubits store the fractional part of the mantissa, in contrast to the $23$ bits used this in the IEEE 754 single-precision format. This is done for illustration purposes, since for real-world computational engineering application $M$ needs to be significantly larger; for example, it is expected that at least $M=8$ is required for most applications. For $E=3$, exponent ${\left(000\right)}_2=0$ defines sub-normal numbers, while ${\left(111\right)}_2=7$ defines “overflow” conditions. For normalized numbers, this leaves the range $1$ to $6$, and therefore ${\mathit{EXP}}_{\mathit{\text{bias}}}=3$ creates a symmetric bias. For this symmetric bias, and assuming $M=4$, the qubit strings $\mid 011\mid 000⟩$ and $\mid 011\mid 111⟩$ define a floating-point number with magnitudes $8/8$ and $15/8$, respectively (where the sign qubit was omitted for clarity). The smallest normalized number represented by qubit string $\mid 001\mid 000⟩$ is 8/32. The smallest non-zero sub-normal number equals $1/32$ and is represented by the qubit string $\mid 000\mid 000⟩$. A key aspect of the present format is the use of an asymmetric bias. This enables the range of numbers that can accurately be presented to be tailored to the considered problem. This was demonstrated for quantum circuit implementation of one-dimensional lattice models for fluid dynamics [16, 17]. For the previously considered examples with $M=4$, an asymmetric bias of ${\mathit{EXP}}_{\mathit{\text{bias}}}=5$ means that the qubit strings $\mid 011\mid 000⟩$ and $\mid 011\mid 111⟩$ define the number $8/32$ and $15/32$, respectively. Also, for this asymmetric bias, the smallest non-zero sub-normal number represented by qubit string $\mid 000\mid 000⟩$ takes on the value $1/128$.

5. Quantum circuits for kinetic energy evaluation

This section considers the squaring of floating-point numbers as required, for example, in the evaluation of kinetic energy of a fluid or a solid object. Here, a one-dimensional flow with velocity $u$ is assumed for illustration purposes. Also, to simplify the circuits, no sign qubits are used, with all real data assumed to be positive. The required operation can then be summarized as follows. For an input $u$ defined as a quantum floating-point number with $M$-qubit representation of the significant ($M-1$ qubits for fractional part), an integer squaring is performed to create a $2M-$bit temporary result. Based on the exponent of $u$ and the exponent bias used, the next step defines the square in terms of the floating-point format. It is in this second step that rounding aspects are to be considered. Following the definition of the square in floating-point format, the mantissa-squaring step is uncomputed, so that the qubit register at completion of the full quantum circuit for floating-point squaring differs from the initial quantum register state only in terms of the qubits defining kinetic energy (squared number) output.

5.1 Performing mantissa squaring

Integer squaring can be implemented in quantum circuits based on a number of different approaches, e.g., Quantum Fourier-based [5, 12], building on the concept of shift-and-add using controlled additions [17] or optimized logic-based approaches. Since the main focus of this work is the definition of the quantum floating-point output with consistent rounding, this aspect is not analyzed further, and optimized logic-based circuits are used for integer squaring. A 4-bit representation of the mantissa of $u$ is considered here $\left(M=4\right)$.

Figure 3 shows the example circuit for the squaring of a 4-bit integer defined in $\mid a3\mid a2\mid a1\mid a0⟩$ (with $a3$ the most significant bit in the binary representation), with the 8-qubit integer result defined in $\mid p7\mid p6\mid p5\mid p4\mid p3\mid p2\mid p1\mid p0⟩$. The quantum circuit shown was designed with minimum circuit width in mind, and the creation of five “garbage” qubits $\mid g0⟩$ to $\mid g4⟩$ was tolerated. Garbage qubits as used here are additional qubits in the quantum circuit used to represent results from intermediate steps in the squaring computation. Assuming that these qubits are initialized in the $\mid 0⟩$ state at the left-hand side of the circuit, their final state on the right-hand side of the circuit may have changed depending on the particular squaring performed.

Figure 3.

Quantum circuit for squaring of an integer defined by $4$ qubits $\mid a3\mid a2\mid a1\mid a0⟩$, with results in $\mid p7\mid \dots \mid p0⟩$ such that $5$ garbage qubits are created.

Based on the quantum circuit shown in Figure 3, a quantum circuit used for mantissa squaring is created that does not create garbage output, but instead uses $5$ ancilla qubits that are initialized as $\mid 0⟩$ and return to $\mid 0⟩$ at the completion of the squaring. As can be seen, the elimination of garbage qubits comes at the cost of increased circuit depth, that is, an increased number of gate operations. The quantum circuit with $17$ qubits is shown in Figure 4.

Figure 4.

Quantum circuit used to compute square of the mantissa of $u$ in floating-point squaring.

In the quantum circuit shown in Figure 4, the $17$ qubits represent the following:

$$\begin{array}{lll}\mid \mathit{qu}3\mid \mathit{qu}2\mid \mathit{qu}1\mid \mathit{qu}0⟩& :& 4\text{qubits defining}4‐\mathrm{bit}{\text{input}}^{‘}{\mathrm{u}}^{’}\\ \mid r7\mid r6\mid r5\mid r4\mid r3\mid r2\mid r1\mid r0⟩& :& 8\text{qubit defining output}\\ \mid \mathit{anc}4\mid \mathit{anc}3\mid \mathit{anc}2\mid \mathit{anc}1\mid \mathit{anc}0⟩& :& 5\text{ancilla qubits}\end{array}$$E4

Using computational-basis encoding [1], the quantum circuit for squaring can be used as follows. The 17-qubit register is first initialized such that a single complex amplitude is non-zero, that is, it is set to $1$. The index of this single non-zero complex amplitude is fully defined by the input integer number, that is, the binary representation of the number defined by $\mid \mathit{qu}3\mid \mathit{qu}2\mid \mathit{qu}1\mid q0⟩$. For an integer defined by $4$ qubits, the $8$ possible outcomes (for a most significant qubit $\mid \mathit{qu}3⟩=\mid 1⟩$) can be summarized as:

$$\begin{array}{llll}u=8& C_{\mathit{\text{in}}}\left[1000|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1000|01000000|00000\right]\\ u=9& C_{\mathit{\text{in}}}\left[1001|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1001|01010001|00000\right]\\ u=10& C_{\mathit{\text{in}}}\left[1010|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1010|01100100|00000\right]\\ u=11& C_{\mathit{\text{in}}}\left[1011|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1011|01111001|00000\right]\\ u=12& C_{\mathit{\text{in}}}\left[1100|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1100|10010000|00000\right]\\ u=13& C_{\mathit{\text{in}}}\left[1101|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1101|10101001|00000\right]\\ u=14& C_{\mathit{\text{in}}}\left[1110|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1110|11000100|00000\right]\\ u=15& C_{\mathit{\text{in}}}\left[1111|00000000|00000\right]& \to & C_{\mathit{\text{out}}}\left[1111|11100001|00000\right]\end{array}$$E5

where $C_{\mathit{\text{in}}}\left[{\mathit{\text{indx}}}_0\right]$ the complex amplitude in the initial state vector with non-zero magnitude at index ${\mathit{\text{indx}}}_0$ represented in binary representation and the left-hand side above. At the completion of the quantum circuit, a single complex amplitude $C_{\mathit{\text{out}}}\left[{\mathit{\text{indx}}}_1\right]$ will have non-zero amplitude at index ${\mathit{\text{indx}}}_1$ defined in binary representation on the right-hand side of the listed results.

5.2 Computing $u^2$ with rounding-to-nearest

For the quantum circuit implementation of squaring $u$, now defined as a floating-point number with $4$ mantissa qubits and $3$ exponents qubits, the following qubits are used:

$$\begin{array}{lll}\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩& :& 3{\text{qubits defining exponent of}}^{‘}{\mathrm{u}}^{’}\\ \mid \mathit{qu}3\mid \mathit{qu}2\mid \mathit{qu}1\mid \mathit{qu}0⟩& :& 4{\text{qubits defining mantissa of}}^{‘}{\mathrm{u}}^{’}\\ \mid r7\mid r6\mid r5\mid r4\mid r3\mid r2\mid r1\mid r0⟩& :& 8\text{qubit defining output}\\ \mid \mathit{anc}4\mid \mathit{anc}3\mid \mathit{anc}2\mid \mathit{anc}1\mid \mathit{anc}0⟩& :& 5\text{ancilla qubits}\\ \mid \mathit{esq}2\mid \mathit{esq}1\mid \mathit{esq}0⟩& :& 3\text{qubits defining exponent of output}\\ \mid \mathit{msq}2\mid \mathit{msq}1\mid \mathit{msq}0⟩& :& 3\text{qubits defining mantissa of output}\\ & & \left({\text{where}}^{‘}\text{hidden}‐{\text{qubit}}^{’}\text{approach is used}\right)\end{array}$$E6

For the considered floating-point squaring, the quantum circuit shown previously in Figure 4 is first applied on the subset of $17$ qubits defined previously. This defines the squaring output in the $8$ qubits $\mid r7\mid r6\mid \dots \mid r0⟩$ with $\mid r7⟩$ defining the most significant bit. This 8-qubit register along with the exponent of the input $u$ is then used to define the output $u^2$ in terms of the quantum floating-point format. Assuming ${\mathit{EXP}}_{\mathit{\text{bias}}}=8$, a quantum circuit implementation of the required logical operations is shown in Figure 5. Here, the dash slices separate sub-circuits intended for different input exponents.

Figure 5.

The circuit shown sets results for $u^2$ in floating-point format for $M=4$ using “rounding-to-nearest” ($E=3$, with ${\mathit{EXP}}_{\mathit{\text{bias}}}=8$).

For the used exponent bias, cases with $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 000⟩$ (i.e., sub-normal input $u$) and $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 001⟩$ are guaranteed to create $u^2$ truncated to $0$. This can be seen from the fact that $u$ defined by $\mid 001\mid 111⟩$ corresponds to a value of $\left(15/8\right)\times 2^{1-8}=15/1024$ and therefore, $u^2$ is smaller than half the smallest non-zero sub-normal number defined by $\mid 000\mid 001⟩$ (or $1/1024$) so that rounding-to-nearest always leads to 0.

The left-hand side of the quantum circuit shown at the top of Figure 5 deals with cases defined by $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 010⟩$. As can be seen, for $u$ inputs leading to $\mid r7⟩=\mid 1⟩$, rounding up can then create the smallest non-zero sub-normal output $\mid 000\mid 001⟩$. The next block of gate operations defines the required logic for $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 011⟩$. As a first step, output mantissa qubits $\mid \mathit{msq}1\mid \mathit{msq}0⟩$ are initialized using the state of $\mid r7\mid r6⟩$. In case rounding-by-truncation would have been used, the work required for this input exponent would be completed. However, for the rounding-to-nearest employed here, cases need to be identified for which rounding up is required, here represented by $\mid \mathit{anc}1⟩=\mid 1⟩$ (i.e., ancilla qubit temporarily set to $\mid 1⟩$). Following a similar approach, the other blocks of gate operations shown in Figure 5 account for $u$ inputs with $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 100⟩$ as well as $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 101⟩$ or $\mid 110⟩$. In all cases, the output mantissa qubits are initially defined according to the rounding-by-truncation (or rounding down) approach, followed by an identification of cases requiring a subsequent rounding up. The rounding up is implemented using multiply-controlled $X$ gate operations creating an increment to mantissa qubits (using hidden-qubit approach) and exponent qubits. For input $u$ with $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 100⟩$, the increment operation applied for cases with rounding up can transform the largest sub-normal number $\mid 000\mid 111⟩$ into the smallest normalized output $\mid 001\mid 000⟩$. For input cases with $\mid \mathit{eu}2\mid \mathit{eu}1\mid \mathit{eu}0⟩=\mid 101⟩$ or $\mid 110⟩$, the output is guaranteed to be a normalized number and therefore the increment operation performed for rounding up can be seen to include controlled-$X$ gate operations on all the output exponent qubits $\mid \mathit{esq}2\mid \mathit{esq}1\mathit{esq}0⟩$ so that output exponent can be incremented by $1$ where required.

Identifying cases that require rounding up is performed as follows:

• If the most significant qubit in $\mid r7\mid r6\mid \dots \mid r1\mid r0⟩$ that is not yet used to define the initial state of the output mantissa qubits is in state $\mid 1⟩$, rounding up is needed if any of the further less significant qubits in $\mid r7\mid r6\mid \dots \mid r1\mid r0⟩$ is in state $\mid 1⟩$;

• Identifying a “tie.” If the most significant qubit in $\mid r7\mid r6\mid \dots \mid r1\mid r0⟩$ that is not yet used to define the initial state of the output mantissa qubits is in state $\mid 1⟩$ with all other less significant qubits in state $\mid 0⟩$, a tie has occurred. In that case, rounding up is applied if the least significant qubit in the initialized output mantissa is in state $\mid 1⟩$, that is, $\mid \mathit{msq}0⟩=\mid 1⟩$.

The approach used here is consistent with the rounding-to-nearest approach used in the IEEE 754 standard.

6. Quantum circuits for floating-point division

Building on the concepts illustrated in the quantum circuit implementation of floating-point squaring with rounding-to-nearest for the output, the more complex example of floating-point division will be detailed. It is shown here that for the floating-point divider, the quantum circuit implementation of logical steps required to perform rounding-to-nearest for the output displays significant similarity with those for the squaring detailed in Section 5.2.

6.1 Non-restoring and restoring integer dividers

First, quantum circuit implementations for non-restoring and restoring integer dividers are discussed, to pave the way for the mantissa division required in the floating-point division circuits discussed later. The integer divider considered here performs the division of a 4-bit integer dividend by a 4-bit integer divisor using the concept of long division. Since the aim is to re-use the resulting quantum circuits later on in the quantum floating-point dividers (where it is assumed that both dividend and divisor are normalized numbers), the assumption is made that $4$ qubits define the dividend $\mid q3i\mid q2i\mid q1i\mid q0i⟩$ with $\mid q3i⟩=\mid 1⟩$, and similarly $4$ qubits define the divisor, that is, $\mid q3d\mid q2d\mid q1d\mid 10d⟩$ with $\mid q3d⟩=\mid 1⟩$.

Before detailing the quantum circuit shown in Figure 6, the underlying principle of a quantum circuit implementation based on long division is summarized. To achieve a 4-bit quotient as output of the division by a 4-bit divisor, it follows that the dividend needs to be a 7-bit integer. Starting from the initial 4-bit (input) dividend, a 7-bit workspace is created by padding three $0$ bits at the least-significant end (effectively multiplying the integer value by eight). The long division then proceeds as follows. Starting from the $4$ most significant bits in the 7-bit workspace, a comparator operator (denoted as $C$) is used to check if the binary value represented by the $4$ bits equals or exceeds the divisor value. If so, the most significant qubit defining the quotient will be set to $\mid 1⟩$. Uncomputing the comparator $C$ (denoted by $U\left(C\right)$) restores the 7-bit register to its state before applying $C$. Then, subtraction by the value of the divisor (denoted by $\mathit{Sub}$) is applied conditionally on the state of the corresponding quotient qubit. These steps are then repeated a further three times, each time shifting the 4-bit sub-string of the workspace the comparators work on by one bit toward the least significant bit. For the illustrated division for 4-bit dividend and divisors, the $4$ repeated steps will fully define the 4-qubit quotient. The final subtraction steps are not needed to define this quotient, as shown in Figure 6. The $\mathit{\text{SWAP}}$ operations shown in Figure 6 are there to arrange the qubits in the correct ordering for successive applications of the comparator $C$, uncomputation of comparator $U\left(C\right)$, and the controlled subtractions. All three operations employ a qubit ordering consistent with Cuccaro-type modulo adders.

Figure 6.

Quantum circuit for non-restoring integer division based on 7-qubit integer register and 4-qubit divisor. Creates 4-qubit output $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$.

For the quantum circuit implementing a non-restoring integer divider defined in Figure 6, the qubits are named as follows:

$$\begin{array}{lll}\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩& :& 4\text{qubits defining}4‐\mathrm{bit}\text{quotient}\\ \mid q3d\mid q2d\mid q1d\mid q0d⟩& :& 4\text{qubits defining}4‐\mathrm{bit}\text{divisor}\\ \mid q4d⟩& :& \text{additional qubit used in}2\mathrm{s}\text{complement representation}\\ \mid q3i\mid q2i\mid q1i\mid q0i⟩& :& 4\text{qubits defining}4‐\mathrm{bit}\text{dividend}\\ \mid \mathit{\text{test}}⟩& :& \text{qubit}\mathrm{us}\mathrm{as}1\mathrm{st}\text{comparator output}\\ \mid c⟩& :& {}^{‘}{\text{carry}}^{’}\text{qubit in Cuccaro}‐\text{type arithmetic}\\ \mid \mathit{qin}2\mid \mathit{qin}1\mid \mathit{qin}0⟩& :& 3\text{additional qubits in}7‐\text{qubit workspace}\end{array}$$E7

The additional qubit $\mid q4d⟩$ is required in the temporary conversion of an unsigned 4-bit representation to a 5-bit 2s complement representation used in the conditional subtractions of the divisor value. The subtractions performed by the sub-circuits termed $\mathit{Sub}$ are based on Cuccaro-type modulo adders. Subtraction instead of addition is achieved by converting the “a” input integer of the adder (notation follows that in Figure 2) into 2s complement representation, and reversing this after the modulo additions is completed. For the controlled subtraction of the divisor defined by $4$ qubits, as illustrated here, a 5-qubit modulo adder is employed involving $11$ qubits, as shown in Figure 6 for the blocks termed $\mathit{Sub}$. As discussed in Section 3, Cuccaro-type modulo adders can directly be derived from the Cuccaro-type full adders detailed previously. A 5-qubit modulo adder can be created using $5$ successive $\mathit{MAJ}$ sub-circuits, followed by $5$ $\mathit{UMA}$ blocks, using the same structure as illustrated for the 3-qubit full adder in Figure 2.

Using the concept of long division, a 4-bit quotient can be obtained by first expanding the 4-bit dividend to a temporary 7-bit workspace defined by $7$ qubits as $\mid q3i\mid q2i\mid q1i\mid q0i\mid 0\mid 0\mid 0⟩,$ that is, $3$ qubits initially in state $\mid 0⟩$ are padded at the back of the original dividend. Using this 7-qubit representation of the dividend guarantees that 4-qubit quotient results with a non-zero most significant bit. As illustrated in Figure 6, long division then creates a quotient defined by $4$ qubits as $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$ using the successive application of comparator operations $C$ (as well as the uncomputation of the comparator operator, $U\left(C\right)$) and controlled subtractions. Here, a $\mid 0⟩$ output of the comparator means that the integer value represented by the 4-bit segment of the workspace considered matches or exceeds the integer value of the divisor. In this case, the subtraction is performed and the corresponding output qubit is set to $\mid 1⟩$. Figure 7 shows the quantum circuit implementation of the comparator operation used here based on the work of Xia et al. [19].

Figure 7.

Example comparator circuit. The result is $\mid 1⟩$ in cases where the integer defined by $\mid q3d\mid q2d\mid q1d\mid q0d⟩$ is greater than the integer represented by $\mid q3i\mid q2i\mid q1i\mid q0i⟩$, and $\mid 0⟩$ in both other cases. For consistency with Cuccaro adders, the ancilla qubit is termed $\mid c⟩$.

It should be noted that the quotient defined by the $4$ qubits $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$ can have $\mid \mathit{qq}3⟩=\mid 0⟩$. In the quantum floating-point dividers considered here, this occurrence of $\mid 0⟩$ for the most significant quotient qubit is to be avoided since, in that case, the least significant output mantissa qubit cannot be defined if the output (quotient) is a normalized number. To prevent this problem, the following changes can be introduced. First, instead of padding $3$ qubits in state $\mid 0⟩$ to the original $4$ qubits defining the dividend, now $4$ additional qubits are added to create an 8-qubit workspace. As shown in Figure 8, the long division then simply involves an additional step (with comparator and uncomputation of comparator, followed by a controlled subtraction) to define a quotient defined by $5$ qubits $\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$. If this integer divider is employed as part of a quantum floating-point divider with 4-qubit mantissa for dividend, divisor, and quotient, then we can use this 5-qubit output as follows. In case $\mid \mathit{qq}4⟩=\mid 0⟩$, the $4$ mantissa qubits of the quotient are taken as $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$. Alternatively, if $\mid \mathit{qq}4⟩=\mid 1⟩$, then $\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1⟩$, so that $\mid \mathit{qq}0⟩$ will be discarded.

Figure 8.

Quantum circuit for non-restoring integer division based on 8-qubit integer register and 4-qubit divisor. Creates 5-qubit output $\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$.

It is important to note that the quantum circuits shown in Figures 6 and 8 are non-restoring division circuits, indicating that upon setting the quotient defined by either $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$ or $\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$, both circuits also change the state of (many) of the other qubits. In applications of integer dividers where such further changes of quantum states are not desirable, a modification of the divider to a restoring version is needed. Figure 9 shows the quantum circuit implementation of a restoring integer divider for 4-bit dividend, divisor, and quotient based on a 7-bit workspace. Comparing the circuit in this figure to the previous non-restoring circuit in Figure 6, it can be seen that the required changes involve setting up three successive controlled additions to un-compute the effect achieved by the corresponding three controlled subtractions used in defining the quotient qubits. A similar modification to create a restoring version of the non-restoring quantum circuit implementation shown in Figure 8 would similarly involve a series of $4$ controlled additions.

Figure 9.

Quantum circuit restoring integer division based on $7$-qubit integer register and 4-qubit divisor. Creates 4-qubit output $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$.

6.2 Extension to floating-point division

We now consider the floating-point division where the dividend, divisor and quotient are all defined in floating-point format with $4$ mantissa qubits $\left(M=4\right)$, and $3$ qubits defining the exponent $\left(E=3\right)$.

Based on the integer divider with the 8-qubit workspace, the mantissa division step for a floating-point divider can be created. The use of the 8-qubit workspace guarantees that even if the 5-qubit quotient resulting from long division has its most significant qubit as $\mid 0⟩$, there are still $4$ quotient qubits left to fully define the 4-qubit output mantissa.

In the context of rounding the output of the floating-point division, it is important to consider that at the end of the long-division steps, used to define $\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$, the 8-bit workspace will be such that the leading $4$ qubits $\mid q3i\mid q2i\mid q1i\mid q0i⟩$ will be in state $\mid 0\mid 0\mid 0\mid 0⟩$, while the $4$ additional qubits $\mid \mathit{qin}3\mid \mathit{qin}2\mid \mathit{qin}1\mid \mathit{qin}0⟩$, which were initialized at $\mid 0\mid 0\mid 0\mid 0⟩$) now define the remainder of the long division.

In the interest of clarity and brevity, divisions leading to quotients defined as normalized floating-point numbers are considered for now. The extension to sub-normal output is discussed later in this section.

As a first step in setting output employing rounding-to-nearest, the output mantissa qubits are initialized using the rounding-by-truncation (or rounding down) approach by considering two different cases. For $\mid \mathit{qq}4⟩=\mid 1⟩$, the $3$ output mantissa qubits (defining the fractional part) $\mid \mathit{mf}2\mid \mathit{mf}1\mid \mathit{mf}0⟩$ are initialized using $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1⟩$. For $\mid \mathit{qq}4⟩=\mid 0⟩$, the $3$ output mantissa qubits $\mid \mathit{mf}2\mid \mathit{mf}1\mid \mathit{mf}0⟩$ are initialized using $\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$.

To introduce rounding-to-nearest for the quotient, the two different cases also require a different treatment:

• For cases with $\mid \mathit{qq}4⟩=\mid 1⟩$, the state of qubit $\mid \mathit{qq}0⟩$ and the state of the remainder of the long-division step defined in qubits $\mid \mathit{qin}3\mid \mathit{qin}2\mid \mathit{qin}1\mid \mathit{qin}0⟩$ together define the type of rounding required. Specifically, $\mid \mathit{qq}0⟩=\mid 0⟩$ means that rounding down is to be used, while for $\mid \mathit{qq}0⟩=\mid 1⟩$, the state of qubits $\mid \mathit{qin}3\mid \mathit{qin}2\mid \mathit{qin}1\mid \mathit{qin}0⟩$ determines whether rounding up is required, a process that also involves identifying a possible “tie,” similar to that described for the floating-point squaring;

• For cases with $\mid \mathit{qq}4⟩=\mid 0⟩$, it is only the state of the “remainder qubits” $\mid \mathit{qin}3\mid \mathit{qin}2\mid \mathit{qin}1\mid \mathit{qin}0⟩$ that defines the required type of rounding. In this case, divisions with an even divisor and those with an odd divisor need to be considered separately in terms of identifying the occurrence of a “tie.”

Clearly, introducing rounding-to-nearest in a floating-point divider using the 8-qubit workspace restoring integer divider is complicated by the significant differences for the cases with $\mid \mathit{qq}4⟩=\mid 1⟩$ versus cases with $\mid \mathit{qq}4⟩=\mid 0⟩$ as an output of the long division.

To address this problem, an alternative approach is now proposed using a workspace extended by a further qubit. Specifically, starting from a 4-qubit string defining the dividend, $5$ additional qubits initiated at state $\mid 0⟩$ are used at the least-significant end of the register. This effectively multiplies the original number represented by $32$, ensures that the required 6-qubit quotient is obtained. Of course, this involves creating an additional step in the long division, but the added complexity is accepted here on the basis of the simplified steps for defining and rounding of the output. As will become clear from the following analysis, this approach enables the required logic for rounding-to-nearest of the output to be implemented in quantum circuits following a similar approach introduced for the floating-point squaring in the previous section.

Figure 10 shows the first part of the quantum circuit implementation for the restoring long division used to define the 6-qubit quotient $\mid \mathit{qq}5\mid \mathit{qq}4\mid \mathit{qq}4\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$. Figure 11 shows the part of the quantum circuit implementation that restores all the qubits not defining the quotient output to their original state.

Figure 10.

Quantum circuit for restoring integer division based on 9-qubit integer register and 4-qubit divisor. Creates 6-qubit output $\mid \mathit{qq}5\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$. Part 1.

Figure 11.

Quantum circuit for restoring integer division based on 9-qubit integer register and 4-qubit divisor. Creates 6-qubit output $\mid \mathit{qq}5\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1\mid \mathit{qq}0⟩$. Part 2.

The key idea now is to use the 9-qubit workspace integer division circuits shown in Figures 10 and 11 for the purpose of the division of the dividend mantissa by the divisor mantissa. In addition to mantissa division, a key role in floating-point division is played by the difference of the dividend of divisor exponents, since this difference largely determines the output exponent (as detailed later).

In the interest of brevity, the quantum circuit implementation considered here includes the following simplifications:

• only positive numbers will be considered here, so there is no need to use qubits defining the sign for dividend, divisor and quotient;

• no qubits are allocated to define the exponent of the dividend and divisor. Instead, three qubits $\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩$ are allocated initialized at $\mid 0⟩$. It is assumed that an operator $\mathrm{\Delta }E$ sets the qubits $\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩$ to contain the binary representation of the difference between the exponent of the dividend and the exponent of the divisor, with ${\mathit{EXP}}_{\mathit{\text{bias}}}$ subsequently added to this difference.

In Figure 12, the quantum circuit implementation of the floating-point divider considered here is shown. The quantum circuit implementation shown assumes that the quotient is a normalized floating-point number. At the end of this section, an extended version without this restriction is presented. Building on the integer divider based on the 9-qubit workspace, the following additional qubits are defined:

Figure 12.

Quantum circuit implementation of floating-point divider assuming a normalized quotient is created.

$$\begin{array}{lll}\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩& :& 4\text{qubits defining the exponent difference}\\ \mid \mathit{ef}2\mid \mathit{ef}1\mid \mathit{ef}0⟩& :& 3\text{exponent qubits for quotient}\\ \mid \mathit{mf}2\mid \mathit{mf}1\mid \mathit{mf}0⟩& :& 3\text{qubits for mantissa}\left({}^{‘}{\text{hidden}}^{’}\mathrm{bit}\text{not stored}\right)\end{array}$$E8

In Figure 12, $\mathit{Div}$ represents the non-restoring part of the integer divider shown in Figure 10. On the right-hand side of the circuit, this divider is uncomputed, as indicated by $U\left(\mathit{Div}\right)$. Also, at the end of the floating-point division, the operator $\mathrm{\Delta }E$ is also uncomputed (shown as $U\left(\mathrm{\Delta }E\right)$) to restore $\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩$ to $\mid 0\mid 0\mid 0⟩$.

The quantum floating-point division as shown in Figure 12 proceeds as follows:

• Operator $\mathrm{\Delta }E$ defines the difference between dividend and divisor exponents (and adds the exponent bias);

• Long division of the mantissa of dividend and mantissa of divisor, shown as operator $\mathit{Div}$ in the quantum circuit;

• Based on the exponent difference set by $\mathrm{\Delta }E$ and stored in qubits $\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩$, the exponent of the floating-point output for quotient defined by $\mid \mathit{ef}2\mid \mathit{ef}1\mid \mathit{ef}0⟩$ is initialized;

• For long divisions resulting in $\mid \mathit{qq}5⟩=\mid 1⟩$, the three qubits $\mid \mathit{mf}2\mid \mathit{mf}1\mid \mathit{mf}0⟩$ defining the quotient mantissa (using hidden-qubit approach) are set using $\mid \mathit{qq}4\mid \mathit{qq}3\mid \mathit{qq}2⟩$. For long divisions resulting in $\mid \mathit{qq}5⟩=\mid 0⟩$, the three qubits $\mid \mathit{mf}2\mid \mathit{mf}1\mid \mathit{mf}0⟩$ are set using $\mid \mathit{qq}3\mid \mathit{qq}2\mid \mathit{qq}1⟩$;

• For the four qubits defining (part of) the remainder of the long division, $\mid \mathit{qin}3\mid \mathit{qin}2\mid \mathit{qin}1\mid \mathit{qin}0⟩$ all in state $\mid 0⟩$, temporarily set the qubit $\mid c⟩=\mid 1⟩$;

• After completing the long division, the qubit $\mid \mathit{\text{test}}⟩$ (in state $\mid 0⟩$) is temporarily in the location of qubit $\mid q4d⟩$ during initialization (due to qubit swap operations performed). The qubit $\mid \mathit{\text{test}}⟩$ will now be set to $\mid 1⟩$ for cases requiring rounding up;

• For cases with $\mid \mathit{qq}5⟩=\mid 1⟩$, rounding up is always needed for $\mid \mathit{qq}1\mid \mathit{qq}0⟩=\mid 1\mid 1⟩$ and cases with $\mid \mathit{qq}1\mid \mathit{qq}0⟩=\mid 1\mid 0⟩$ and $\mid c⟩=\mid 0⟩$. Similar to the floating-point squaring discussed previously in Section 5.2, a tie occurs for $\mid \mathit{qq}5⟩=\mid 1⟩$, $\mid \mathit{qq}1\mid \mathit{qq}0⟩=\mid 1\mid 0⟩$ and $\mid c⟩=\mid 1⟩$. Then $\mid \mathit{mf}0⟩=\mid 1⟩$ (set by $\mid \mathit{qq}2⟩=\mid 1⟩$) determines cases with rounding up.

• For cases with $\mid \mathit{qq}5⟩=\mid 0⟩$, rounding up is needed for $\mid \mathit{qq}0⟩=\mid 1⟩$ and $\mid c⟩=\mathit{ket}0$, while a tie is found for $\mid \mathit{qq}0⟩=\mid 1⟩$ and $\mid c⟩=\mathit{ket}1$. The tie-break is decided by the state $\mid \mathit{mf}0⟩=\mid 1⟩$ (set by $\mid \mathit{qq}1⟩=\mid 1⟩$ in this case);

• The following $6$ multiply-controlled $X$ operations apply the rounding up by incrementing the mantissa and where needed the exponent;

• The remaining operations perform uncomputation to restore the qubits not defining the quotient output in their original state.

From this outline, it is clear that the fundamental steps involved in defining rounding-to-nearest for the floating-point divider output demonstrate strong similarity with the corresponding steps in the floating-point squaring.

In the final part of this section, an extended quantum circuit implementation of the divider shown in Figure 12 is considered that can also create quotients defined as sub-normal floating-point numbers. As shown in Figure 13, the first change involves making the quantum gate operations used to initialize $\mid \mathit{ef}2\mid \mathit{ef}1\mid \mathit{ef}0⟩$ and $\mid \mathit{mf}2\mid \mathit{mf}1\mid \mathit{mf}0⟩$ and the subsequent rounding conditional on the difference of the dividend and divisor exponents. Specifically, in Figure 13, the qubit $\mid q3i⟩$ (guaranteed to be in state $\mid 0⟩$ after long division) is temporary set to $\mid 1⟩$ for cases where the quotient is guaranteed to be a normalized floating-point number. This qubit is then used as (additional) control qubit for the gate operations defining the exponent and mantissa qubits for quotient as well as the subsequent rounding operations. As can be seen, the register $\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩$ is extended to four qubits by adding $\mid \mathit{de}3⟩$, since including the capability to output sub-normal quotients means that the difference in exponents defined by $\mathrm{\Delta }E$ now includes negative numbers. Negative numbers are represented using 2’s complement formulation, requiring the additional qubit.

Figure 13.

Quantum circuit implementation of floating-point divider, with quotient defined as either normalized or sub-normal number. Part 1.

The left-hand side of the quantum circuit shown in Figure 14 considers cases defined by $\mid \mathit{de}3\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩=\mid 0\mid 0\mid 0\mid 1⟩$. For the case a symmetric bias $({\mathit{EXP}}_{\mathit{\text{bias}}}=3$ for $E=3)$ is employed, this means that the exponent of the divisor is greater than the exponent of the dividend by a factor of 2. For long divisions leading to results with $\mid \mathit{qq}5⟩=\mid 1⟩$, the quotient is always a normalized number. The largest fraction that needs to be represented is $\left(15/8\right)/4=15/32$, which can be exactly defined as $\mid 001\mid 111⟩$ in floating-point format. The smallest fraction that needs to be represented is then $\left(8/15\right)/4$ (rounded down to $4/32$ or $\mid 000\mid 100⟩$ in floating-point format).

Figure 14.

Quantum circuit implementation of floating-point divider, with quotient defined as either normalized or sub-normal number. Part 2.

The right-hand side of the quantum circuit shown in Figure 14 considers cases defined by $\mid \mathit{de}3\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩=\mid 0\mid 0\mid 0\mid 0⟩$. The smallest fraction that needs to be represented for ${\mathit{EXP}}_{\mathit{\text{bias}}}=3$ is then $\left(8/15\right)/8$ (rounded down to $2/32$ or $\mid 000\mid 010⟩$ in floating-point format). Similarly, the largest fraction is $\left(15/8\right)/8$ (rounded up to $8/32$ or $\mid 001\mid 000⟩$ in floating-point format). This shows that using the rounding-to-nearest rounding mode with the required rounding up for the largest fraction is the reason a normalized output results for that case. Rounding-by-truncation creates the sub-normal $\mid 000\mid 111⟩$ for this largest fraction.

In Figure 15, the final two possible results for the difference in exponents of dividend and divisor are considered, followed by the uncomputation of the long division and un-computation of $\mathrm{\Delta }E$, so that all qubits not used to define quotient output have been restored to their original state. The left-hand side of the quantum circuit shown in Figure 15 considers cases defined by $\mid \mathit{de}3\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩=\mid 1\mid 1\mid 1\mid 1⟩$ (or ${}^{‘}-1^{’}$ in 2’s complement). For the case a symmetric bias is employed, this means that the exponent of the divisor is greater than the exponent of the dividend by a factor of 4. The smallest fraction that needs to be represented is then $\left(8/15\right)/16$ (rounded down to $1/32$ or $\mid 000\mid 001⟩$ in floating-point format). Similarly, the largest fraction is $\left(15/8\right)/16$ (rounded up to $4/32$ or $\mid 000\mid 100⟩$ in floating-point format). The right-hand side of the quantum circuit shown in Figure 15 considers cases defined by $\mid \mathit{de}3\mid \mathit{de}2\mid \mathit{de}1\mid \mathit{de}0⟩=\mid 1\mid 1\mid 1\mid 0⟩$ (or ${}^{‘}-2^{’}$ in 2’s complement). In that case, the largest fraction to be represented is $\left(15/8\right)/32$, with rounding-to-nearest requiring rounding up to $2/32$ or $\mid 000\mid 010⟩$ in floating-point format. For the smallest fraction $\left(8/15\right)/32$, the qubit $\mid \mathit{qq}5⟩$ will have state $\mid 0⟩$, but the rounding-to-nearest requires rounding up to $1/32$ or $\mid 000\mid 001⟩$ in floating-point format. This means that only the required rounding up needed for the smallest fraction avoids truncation of the output to 0.

Figure 15.

Quantum circuit implementation of floating-point divider, with quotient defined as either normalized or sub-normal number. Part 3.

Comparing the quantum circuit implementations shown in Figures 13–15 to the quantum circuits in Figure 12 clearly shows the significant additional complexity created by dealing with potential sub-normal output. However, the steps involved in performing the rounding-to-nearest of the output remain essentially the same.

7. Conclusions

Two applications of quantum arithmetic involving a reduced-precision floating-point representation were analyzed in detail, with a particular focus on how the floating-point output can be defined using a rounding-to-nearest approach similar to the IEEE-754 standard. The analysis shows that despite the obvious differences in the arithmetic involved in the squaring of a number and the division of two numbers, the quantum circuit implementation of the logic required for rounding-to-nearest for both applications shows significant similarities in the modular designs used here. This is an important finding for future work, in particular when quantum circuit compilation techniques are to be used for the automated definition of quantum arithmetic circuits using a larger number of mantissa and/or exponent qubits than in the examples shown here. In future work, the application to a wider class of arithmetic operations will be considered.

Abbreviations

QC	quantum computing
CFD	computational fluid dynamics
IEEE	Institute of Electrical and Electronics Engineers