Secure Smart Card IP

Abstract

This book chapter highlights the embedded system security by designing a secure smart card IP. Indeed, the smart card is recognized as a privileged means of both storing confidential information and performing secure transactions. Its main role comes from the security it provides inside the system it is a part of. The specification and development of the elaborate smart card architecture are very delicate steps that require the pooling of strong competences in computer security, electronics, and also cryptography. The developed secure smart card IP model is based on the Gaisler LEON2 processor. To ensure a maximum level of security and optimal performance, a hardware integration of cryptographic mechanisms through instruction extensions was carried out. The integrated mechanisms allow for ensuring confidentiality, hashing, random number generation, and digital signature. The proposed smart card IP was implemented on a reconfigurable FPGA platform, and then on ASIC using 40 nm CMOS technology. A surface area of 1.08 mm2 with a consumed dynamic power of 23 mW for a frequency of 13.5 MHz was achieved.

1. Introduction

Smart cards, as embedded systems utilized by consumers, play a crucial role in safeguarding the security of their respective systems. However, the potential of smart cards has significantly expanded with the introduction of multi-application cards, offering a diverse range of services such as GSM, electronic wallets, and loyalty programs [1]. To ensure confidentiality, security, and authentication, the integration of cryptographic mechanisms into smart cards is of utmost importance.

With the increasing diversity and openness of smart card systems, a race ensues between smart card developers and attackers, aiming to discover vulnerabilities and bolster security measures. Consequently, it becomes imperative to continuously update smart card security in order to counter hardware attacks effectively. This necessitates the implementation of robust countermeasures capable of detecting and thwarting attempts to manipulate the card’s behavior or exploit techniques like spatial, temporal, or information redundancy [2].

The central objective of this chapter is to design a secure smart card Intellectual Property (IP). This endeavor encompasses the careful selection of appropriate hardware components, comprising essential blocks, and the development of an efficient interconnection system. Throughout the design process, thorough consideration is given to performance criteria, adherence to industry standards, specific characteristics pertinent to smart cards, and any applicable constraints. Each individual block of the design will undergo meticulous evaluation at multiple stages of the design chain, thereby ensuring the integrity and efficacy of the overall system.

2. State of the art and objectives

A smart card is a plastic card that contains an electronic circuit capable of securely manipulating information, such as storing and calculating. The evolution of smart card technology has been marked by various significant dates. In 1974, Roland Moreno, leading a research team for Innovation, created the first memory-based smart cards. In 1977, the memory card advanced into a microprocessor card. In 1980, the French company Bull produced the CP8, the first microprocessor card used for early trials of bank cards [3]. By 1984, the first health smart card was introduced, and the micro-module card emerged in the same year to create the first telephone cards. In 1996, the publication of the Java Card 1.0 specification by Schlumberger simplified smart card programming. The following year, Bull, Sun, and Gemplus collaborated with Schlumberger to found the Java Card Forum, marking the beginning of smart card standards and specifications [4].

3. Application areas

The fields of application of smart cards have continued to grow. Initially designed as simple token carriers, such as telephone cards, they first became secure document carriers (health card) before becoming mobile code carriers (Java Card). The major application areas of microprocessor cards are [5]:

• Telecommunications: with SIM cards for GSM mobile networks, and telephone cards

• Banking: with EMV payment cards and electronic wallets such as Moneo

• Security and access control: with electronic identity cards, biometric passports, pay-per-view television, and contactless payment with the RATP’s Passe Navigo card

• Health: with the French Vitale card and the future NetCards card in Europe.

4. Standards and characteristics

4.1 Standardization level of smart cards

The level of standardization of the smart card is remarkable. Whether it is a bank card or a SIM card, it will be recognized by the reader device (mobile phone or bank ATM). Three types of parameters are standardized: physical parameters that set the size and positions of the chip and its contacts, electrical parameters specifying the supply voltages, various pins, and software parameters defining the communication mode with the card.

The standardization of smart cards has resulted in the publication of international standards. The classic or contact smart card is standardized by the ISO7816 standards (-1,-2,-3, and -4). These standards define respectively, the physical characteristics of the card, the position and pinouts, the electrical levels, and the various basic commands [6]. On the other hand, contactless cards are governed by the ISO14443 standards (-1,-2, and -3). They contain specifications for the part, the electrical interface, as well as the communication and collision management protocol [7].

4.2 Different types of smart cards

The cards are divided into two families: contact cards (memory or microprocessor) and contactless cards [8].

4.3 Contact cards

A contact smart card has eight visible connectors. Three connectors are reserved for future use (RFU: Reserved for Future Use). The electrical power supply (pins VCC and VSS, usually 5 V) and the clock at around 3.5 MHz (Clock) are included. The smart card can be rebooted by the reader by briefly setting the RESET pin to 0 (hot reset). Communication between the chip and the reader can be in serial mode, bit by bit, on the input/output pin. The Vpp pin was previously used for programming the chip (Figure 1). There are two types of contact smart cards: memory cards and microprocessor cards [9].

Figure 1.

Pinout of a contact smart card.

4.3.1 Memory cards

This type of card consists essentially of an EEPROM memory that does not require high programming voltage. This memory is generally programmable only once (OTPROM: One Time Programmable). Memory cards are used in the field of telephony where the programming principle is irreversible.

4.3.2 Microprocessor cards

This type of smart card is composed of a chip used to perform complex functions. It can be considered as a mini-computer that includes all the components that are usually found on a PC motherboard on a system-on-chip (SoC). This chip includes a microprocessor (8-bit, 16-bit or 32-bit), a memory area (ROM, EEPROM, RAM), as well as several calculation devices used, among others, for cryptography (such as RSA, DES, Random, etc.) and a data transmission interface (UART). This chip has a surface area of less than 25 mm². They are particularly used in bank cards, health insurance cards, but also SIM cards (Subscriber Identity Module) used in mobile phones.

4.4 Contactless cards

Contactless smart cards or RFID (Radio Frequency Identification Device) cards are not directly connected to the reader by a physical contact; the connection is made through an electromagnetic field. To function, the contactless card must be placed at a distance of less than 3 cm from the reader. To be powered, the card uses inductive or capacitive coupling. The clock used for card synchronization can be internal, and the inputs/outputs are made by modulation of the power supply. This type of card is used for access control systems, animal identification, containers, consumer products, etc.

4.5 Combined cards (Combi)

Combi cards, also referred to as dual interface cards, are cards that integrate contact and contactless technologies onto the same chip. They possess two distinct interfaces that enable their use in both contact and contactless modes, making them versatile and ideal for various applications like access control, public transportation, and electronic payment systems. The contact interface provides high security, while the contactless interface offers convenience and faster usage. Due to their ability to provide a seamless transition between contact and contactless modes, the use of combined cards is increasingly prevalent.

5. Steps of manufacturing

The manufacturing process of the electronic chip follows the same process as an integrated circuit, starting from the design and development phase, to the extraction of the wafer using specific CAD tools. These tools are used to make etchings on the wafer to produce the intended functionality of the chip. After the testing phase, the sawing process and finally the extraction of the chips are initiated [10].

The assembly of the chip onto the metal part of the card is illustrated in Figure 2. The legs of the chip are bonded to those of the protective module (side A) using a low-resistance wire. Side B represents the external contact support of the chip ensuring the connection with the reader.

Figure 2.

Chip module realization.

The chip module is then inserted into the PVC card. A cavity is excavated to fix the chip module (Figure 3).

Figure 3.

Assembly processes for smart cards.

Pour the manufacturing of the contactless smart card, the steps are similar to the contact smart card. However, an antenna is needed to facilitate data exchange by chemical etching of copper or aluminum on the PVC card.

6. Industrialized smart cards

The smart card industry has been constantly evolving in recent years thanks to the advancement of semiconductor technology as well as the widespread use of smart cards in modern society, such as in e-commerce, telecommunications, identification, access control, health, banking, entertainment, and transportation, etc.

The architectures proposed by different manufacturers depend on the application domains to which they are dedicated. The processor speed and memory block sizes (ROM, RAM, and EEPROM) integrated into the card’s chip vary from one manufacturer to another. Industrialized cards may include 8/16/32-bit RISC architecture processors, clocked at frequencies ranging from 4 MHz for older versions up to 60 MHz for recent versions (Table 1) [11, 12].

Manufacturer	Year	ROM (ko)	E^2PROM (ko)	Flash (ko)	RAM (ko)	Processor
Motorola SC01/MAM01	1983	1,6	1 (EPROM)	NA	36o	6805, 8bits, 4 MHz
TRT-Philips P83C852	1995	16	4	NA	256o	80C51, 8 bits, 10 MHz RSA/DSA/DES
Atmel AT90SDC100	2010	128	36	NA	6	AVR, 8/16 bits RISC, biprocessor, 30Mhz 3DES/AES/TRNG
Infineon SLE78CX1440P	2010	288	144	NA	8	Dual 16 bits, 33 MHz RSA/EC/AES/3DES/SHA2/TRNG
ST Microelectronics ST33J2M0	2016	NA	NA	2048	50	ARM, 32-bit RISC, 60 MHz AES/DES,/Nescrypt co-processors
Samsung S3FT9MH_ID	2019	40	NA	500	14	SecuCalm16-bit 3DES/AES/RSA/ECC

Table 1.

Characteristics of some industrialized smart cards.

Secure smart cards also exist in the global market with the integration of cryptographic modules ensuring the security of information stored in the chip as well as securing transmitted data.

7. Proposed smart card IP

The architecture consists of a 32-bit microprocessor with a 5-stage pipeline, which forms the core of our IP, memory blocks (ROM, RAM, EEPROM), a 32-bit crypto-processor (ECDSA, AES, RNG, SHA), and a communication interface (UART) connected to the card contact, ensuring communication with the reader (Figure 4).

Figure 4.

Proposed IP smart card architecture.

During the design of the proposed smart card, standard mechanical and electrical constraints are taken into consideration [1]:

• Hardware Configuration: 32 KB ROM (for OS), 64 KB EEPROM (machine codes, information), and 8 KB RAM (data).

• ISO7816-1/2 Standards: surface area of 25 mm², thickness of 200 μm, and dimensions of 85x54x0.76 mm.

• ISO7816-3 Standard: frequency range between 1 and 5 MHz for contact cards and 13.56 MHz for contactless cards according to the ISO14443 standard.

7.1 Choice of the processor

Currently, there is a wide range of dedicated processors for smart cards in the semiconductor market. Among this wide range, we can mention the AVR processor from Atmel, SecuCalm16 from Samsung, sc300, Cortex M0/3, and ARM7TDMI from ARM [13], the ST22XJ64 from STMicroelectronics, and SLE 88CX720P from Infineon Technologies [11, 12, 13, 14, 15, 16, 17, 18, 19].

In recent years, Gaisler Research, under contract with the European Space Agency (ESA), developed a processor called LEON2 [20]. It is used in embedded systems on board satellites. The LEON2 processor is available in two versions: Standard and Fault-tolerant. This processor is defined by a freely usable IP described in VHDL RTL (Figure 5).

Figure 5.

LEON2 processor architecture.

The interest in the Leon2 processor is demonstrated by the recent production by ATMEL of a component for space applications based on this processor [19]. It is also used in an increasing number of applications thanks to its characteristic of being a freely usable IP. LEON2 was the core of an identification portable system described in [21, 22], and it has also been used to manage a wireless communication application in [23].

Apart from the license, several characteristics led to the choice of LEON2 as the core of our application:

• 32-bit RISC architecture with a 5-stage pipeline;

• Configurable instruction/data cache memories;

• A wide variety of possible configurations;

• Easy porting to different hardware targets;

• A UART interface for data transmission and reception;

• A memory controller that can reach 32-bit addresses and data;

• Possibility of adding new applications through its coprocessor.

7.2 Cryptographic mechanisms

An electronic smart card, whether it is a SIM card, credit card, access card, transportation card, or health card, includes a microprocessor that can store sensitive information. Hence the need to integrate security mechanisms and cryptographic means to ensure that information has not been altered during communication (integrity), to avoid disclosure of their content to third parties (confidentiality), and to identify the author of a document or transaction (authentication).

Modern electronic systems such as smart cards increasingly incorporate components called IPs that can be inserted into any type of design and which provide certain functionalities whose complexity can reach the heart of the processor. The data path of the chosen LEON2 processor is 32-bit, hence the need to adapt the different cryptographic modules. In this work, four IPs providing cryptographic mechanisms are proposed: SHA_1, RNG, ECDSA, and AES. The architectures of the developed IPs are 32 bits. Constraints related to the smart card are taken into consideration during the design of these IPs, which are speed, surface area, and power consumption.

7.2.1 Integrity mechanism

Integrity is a technique used to preserve the integrity of information. It is ensured by a function called hashing, which generates a fingerprint (or hash) of a message. The main functionality of hashing is to verify that the message received by the recipient has not been altered during transmission. This mechanism is also used for digital signature of the message. In this work, the SHA (Secure Hash Algorithm) hashing standard was used. It was designed by the United States National Security Agency (NSA) and published by the National Institute of Standards and Technology (NIST) in 1993. The SHA_1 hashing algorithm generates a 160-bit compressed output from a message of length less than 264-bits [24] with a block size of 512 bits. The first step of this algorithm is to fill or add (Padding) bits to the message M in such a way that the length of the resulting message is a multiple of 512 bits. Then, 80 logical functions defined on words and 80 32-bit constants are performed. These functions produce 32-bit words as output and take three 32-bit words as input [24]. The SHA_1 hashing function is described by a 32-bit architecture as follows (Figure 6).

Figure 6.

32-bit SHA-1 function architecture.

The message to be hashed is loaded in blocks of 32-bits through the input interface. Then, the words are processed on 32-bits. Finally, an output interface generates 5 blocks of 32-bits constituting the hash (160-bits).

7.2.2 Random number generator mechanism

Secure random number generation (RNG) is an essential function in cryptography and for computer security in general. Cryptographic mechanisms are public, and their security is based on the secrecy of the encryption key (Kerckhoffs’ principle). This key must be unpredictable and generated automatically to prevent the possibility of disclosure by an unauthorized third party. Modern cryptographic systems, such as digital signatures, rely heavily on random number generators for producing encryption keys [25].

A random number generator takes an input value, called a seed, and produces an output number that is the result of a computational algorithm. These functions are generally resource-intensive and time-consuming. Pseudo-random generators involve applying a non-linear function by combining several linear feedback shift registers (LFSR) of different sizes.

In this work, the pseudo-random generator W7, which is a standard for GSM communication, was used for key generation due to its performance (speed, complexity, and low power consumption). It is a stream cipher algorithm published in April 2002 by Thomas, D. Anthony, T. Berson, and G. Gond. The internal architecture of W7 consists of three Linear Feedback Shift Registers (LFSR) of respective lengths 38, 43, and 47 bits with periods of 2^38-1, 2^43-1, and 2^47-1. Modifications were made in this manuscript to generate keys of size 163 bits to adapt to the datapath of LEON2. Specifically, each register was subdivided into two 32-bit registers. An output interface is used to group the randomly generated bits into 6 blocks of 32 bits to generate a random key of 164 bits (Figure 7).

Figure 7.

32-bit W7 random number generator architecture.

7.2.3 Authentication mechanism

Operations such as bank transactions, personal authentication, and access to workplaces require the signature of the concerned person. Especially, when they are conducted via an open system like the internet. Hence arises the need to design digital signature mechanisms for the authentication of individuals and companies making purchases or sales over the internet.

Digital signature seeks to digitally mimic a handwritten signature. It consists of a string of bits that depends on the message and a secret key known only to the signer. In practice, digital signature schemes use a hash function that generates a digital fingerprint of a message m to be signed.

There are several digital signature standards that have been developed, such as DSA (Digital Signature Algorithm), digital signature based on the RSA algorithm (Rivest, Shamir, and Adleman), and digital signature based on elliptic curves (ECDSA) which appear in standards ANSI X9.62, FIPS 186-2, IEEE 1363-2000, and ISO/IEC 15946-2 [26]. This scheme, known to be safe and efficient for data authentication, has been used since 2000 by many banks for customer authentication, having key sizes of the order of 163, 271, and 571 bits. It is dedicated to support with specific constraints for smart cards. The 32-bit architecture of the ECDSA digital signature scheme is illustrated by Figure 8.

Figure 8.

32-bit ECDSA based digital signature architecture.

The proposed architecture consists of a SHA_1 hash block, a random number generator (RNG), a library of arithmetic operators over the Galois field GF(2n), and modular operations (inversion, multiplication, and addition) based on 32-bit architectures. This library is necessary to perform operations on elliptic curves as well as scalar multiplication KP, which represents the basic operation for the elliptic curve digital signature algorithm (ECDSA). The ENABLE signal initiates data input. The clock signals CLK and RESET enable the block to be synchronized, and the DONE signal indicates the end of the operation. A control unit is responsible for activating/deactivating the key pair generation process, as well as signature generation/verification.

7.2.4 Confidentiality mechanism

The confidentiality mechanism ensures that information is made unintelligible to unauthorized individuals, entities, and processes.

In this work, the AES (Advanced Encryption Standard) algorithm is chosen to secure data stored in the smart card. It is a block cipher encryption/decryption algorithm, where messages are encrypted in blocks of 128 bits (16 bytes) with key sizes of 128, 192, or 256 bits. The key size defines its level of security, with larger key sizes providing higher security levels [27]. This algorithm has been chosen to be fully operational and secure in any type of environment, which encouraged us to opt for AES with a 128-bit key to ensure the confidentiality service of the smart card. The choice of this algorithm meets many criteria such as its robustness against potential attacks, high processing speed, low resource and memory requirements, and ease of implementation (SP Network) with great flexibility.

In the remainder of this chapter, we have chosen AES with a 128-bit key in its version with 10 rounds. Initially, the plaintext is combined with the first round key K0, equal to the key, through the ADDRoundKey function. Each of the first nine rounds consists of four transformations: SubBytes (4 32-bit SB (i) blocks), ShiftRows, MixColumns, and ADDRoundKey. The last round consists of the same functions as a regular round, except for the MixColumns transformation.

The 32-bit architecture of the AES algorithm is described by Figure 9. An Input_Buffer input buffer allows loading the message to be encrypted (or decrypted) in 32-bit blocks. The 128-bit key is loaded onto 4 32-bit blocks. For decryption, the InvSubBytes (4 32-bit InvSB (i) blocks), InvShiftRows, and InvMixColumns functions are used. A control unit manages the activation and deactivation of the different blocks. An Output_Buffer output buffer allows the encrypted message to be returned in 4 32-bit blocks.

Figure 9.

32-bit architecture of encrypt/decrypt AES algorithm.

8. Modified architecture of Leon2 processor

Modifications were made to the block diagram of the Leon2 processor by adding a crypto-processor and external memories (PROM, SRAM, and EEPROM). These different blocks were developed in the previous sections. Unlike software implementation, which suffers from poor performance, the hardware implementation of cryptographic primitives is recognized to be more efficient in terms of speed, memory usage, and power consumption for embedded systems.

8.1 Cryptographic instructions set extension of the LEON2 processor

A variety of work is focused on improving the security of processors and aims to extend cryptographic instructions. The work described in [28, 29] presents sets of elliptic curve instructions that have been incorporated into a variety of processors. In publications [30, 31, 32, 33], the authors focused on extending instructions for a random number generator, cryptographic modules, symmetric cryptosystems, and the AES algorithm. Hardware implementation of cryptographic primitives is recognized to be more efficient compared to software implementation, in terms of speed, occupied surface, and power dissipated for embedded applications. Hardware implementation also ensures a higher level of security, as a circuit cannot be easily attacked. Hence, there is an interest in hardware implementation in the continuation of our work.

In this section, we will present the principle of integrating new instructions into the core of the LEON2 processor to support the developed cryptographic mechanisms (RNG, SHA, ECDSA, and AES). To achieve this, the entire unit (IU) of the LEON2 is extended by integrating cryptographic instructions through coupling hardware IPs to the processor’s data path to extend its instruction set (See Figure 10).

Figure 10.

Modified architecture of Leon2 integer unit.

There are several return paths from the different stages to the decoding and execution stages. The memory stage is connected to the data cache. The cryptographic unit (CU) grouping cryptographic primitives extensions is described in previous sections. The cryptographic unit is implemented in parallel with the “ALU/Shifter” unit. The operands “op1” and “op2” of the cryptographic unit can be blocked at the input of the ALU/Shifter, as long as this unit is active. There are two input registers “rs1.data” and “rs2.data”. Additional multiplexers on the return paths and output paths prevent the propagation of critical data.

8.2 Proposed instructions

The LEON2 processor is a 32-bit SPARC V8 RISC architecture that has different instruction formats with three and two inputs and one output operand.

8.2.1 SHA_1 instruction

The SHA_1 instruction consists of a 32-bit operand rs1 for inputting the message to be hashed in 32-bit blocks. The result is stored in the destination register rd on 32 bits. The principle of this instruction is shown in Figure II.22. The format of this instruction is as described by Eq. (1).

$$\mathit{SHA}-\mathit{1}\mathit{\text{rs1}}\mathit{rd}$$E1

8.2.2 RNG instruction

The RNG instruction is a hardware instruction used to generate random numbers, and it does not take any operands. The result of this instruction, a 32-bit random number, is stored in the destination register rd. The format of the instruction is simply (Eq. 2).

$$\mathit{RNG}\mathit{rd}$$E2

8.2.3 ECDSA instruction

The proposed instructions for key initialization, generation, and verification of ECDSA digital signature are illustrated in Eqs. (3)–(5).

$$\mathit{\text{ECDSA}}\_\mathit{\text{INIT}}\_\mathit{KEY}\mathit{\text{rs1}},\mathit{\text{rs2}},\mathit{rd}$$E3

$$\mathit{\text{ECDSA}}\_\mathit{\text{SIGrs1}},\mathit{\text{rs2}},\mathit{rd}$$E4

$$\mathit{\text{ECDSA}}\_\mathit{\text{VERIFY rs1}},\mathit{\text{rs2}},\mathit{rd}$$E5

These instructions have two source operands rs1, rs2, and one destination operand rd for the result. These three registers, predefined by the SPARC V8 processor core, have a size of 32 bits. The calculation parameters are entered in blocks of 32 bits. Therefore, to enter operands of 163 bits, 6 blocks of 32-bit size each are required. The result is stored in the destination register rd of 32-bit size.

8.2.4 AES instruction

The cryptographic instructions AES_ENC and AES_DEC (Figure II.25) use three registers: two for the source operands and one for the result. Their syntax is as presented in Eqs. (6) and (7):

$$\mathit{AES}\_\mathit{ENC}\mathit{\text{rs1}},\mathit{\text{rs2}},\mathit{rd}$$E6

$$\mathit{AES}\_\mathit{DEC}\mathit{\text{rs1}},\mathit{\text{rs2}},\mathit{rd}$$E7

9. Hardware implementation results

9.1 Implementation on FPGA platform

In this section, the synthesis results of the cryptographic instruction set extension are performed using the Xilinx ISE tool on the VirtexV FPGA platform (XC5VFX70) and are given in Table 2. The characteristics of the different solutions developed are expressed in terms of frequency, LUTs Slice and FFs Lut pairs used which allows us to analyze the suitability of the proposed solutions for the smart card.

Module	Frequency Max. (MHz)	Occupation
		LUTs Slice	FFs Pairs
IP+ none	108.242	7100	6619
IP + AES_Enc	111.481	7875	8407
IP + AES_Dec	114.364	8292	9030
IP + RNG	109.459	7016	7835
IP + SHA_1	111.481	7190	8220
IP + ECDSA_INIT_KEY	114.199	20,545	23,290
IP + ECDSA_SIG	90.645	25,450	24,531 slice register
IP + ECDSA_VERIFY	110.189	42,431	25,527

Table 2.

Performance of smart card IP with modified Leon2 processor core.

9.2 Implementation of ASIC

Logical synthesis consists of transforming an RTL description into an interconnected network of logic gates that perform the desired functions. The system to be designed is decomposed into combinational logic and memory blocks. The SYNOPSIS Design Compiler software allows for synthesis and optimization using the DESIGN-ANALYZER tools (in graphical mode) and DC-SHELL (in command-line mode). During the optimization phase, the tool uses two constraint models: implicit constraints (imposed by the technology library) and explicit constraints imposed by the user. The output result is a logical netlist represented in Verilog format. This format is also used to transport the netlist from the synthesis tool to the placement and routing tools.

The synthesis of the smart card IP is carried out with timing constraints for the 40 nm target technology. For the frequency ranges imposed by smart card standards, the proposed IP occupies an area of approximately 1.08 mm² with a dynamic power dissipation of no more than 23 mW for a frequency of 13.5 MHz.

10. Conclusions

In this chapter, we have studied smart cards as a type of consumer embedded systems. Their main role comes from the security provided by smart cards inside the system to which they belong. After a thorough study of smart cards, the LEON2 processor from Gaisler was selected to develop a smart card IP. A hardware solution to emerging data security problems was presented, with cryptographic IPs providing confidentiality, hashing, random number generation, and digital signature using a 32-bit data path to meet the bus size of most existing smart card architectures on the market. These cryptographic functions were incorporated into the LEON2 processor instruction set, and external memory blocks were also integrated to design the proposed smart card IP.

To demonstrate our IP, we opted for hardware implementation on an FPGA platform, which provides a prototyping and evaluation support. Then, implementation on ASIC with 40 nm CMOS technology was carried out.